XC2VP7 XILINX [Xilinx, Inc], XC2VP7 Datasheet - Page 121

• Manufacturer Part Number: XC2VP7
• Description: Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Complete Data Sheet
• Manufacturer: XILINX [Xilinx, Inc]

Table 62: Package Skew
Table 63: Sample Window
DS083 (v4.7) November 5, 2007
Product Specification
Notes:
1. These values represent the worst-case skew between any two balls of the package: shortest flight time to longest flight time from Pad
2. Package trace length information is available for these device/package combinations. This information can be used to deskew the
Notes:
1. This parameter indicates the total sampling error of Virtex-II Pro DDR input registers across voltage, temperature, and process. The
2. These measurements include:
Package Skew
Sampling Error at Receiver Pins
to Ball (7.1ps per mm).
package.
characterization methodology uses the DCM to capture the DDR input registers’ edges of operation.
These measurements do not include package or clock tree skew.
-
-
-
-
CLK0 and CLK180 DCM jitter
Worst-case duty-cycle distortion, T
DCM accuracy (phase offset)
DCM phase shift resolution
Description
Description
R
(1)
(1)
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
DCD_CLK180
Symbol
T
SAMP
T
Symbol
PKGSKEW
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Device
All
XC2VP2FF672
XC2VP4FF672
XC2VP7FF672
XC2VP7FF896
XC2VP20FF896
XC2VPX20FF896
XC2VP20FF1152
XC2VP30FF896
XC2VP30FF1152
XC2VP40FF1152
XC2VP40FF1148
XC2VP50FF1152
XC2VP50FF1148
XC2VP50FF1517
XC2VP70FF1517
XC2VP70FF1704
XC2VPX70FF1704
XC2VP100FF1704
XC2VP100FF1696
Device/Package
0.50
–
7
Speed Grade
0.50
–
6
Value
104
102
101
106
112
100
101
101
101
100
92
93
93
86
92
88
97
95
86
0.50
–
5
Module 3 of 4
Units
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
Units
ns
50