XC2VP7 XILINX [Xilinx, Inc], XC2VP7 Datasheet - Page 120

no-image

XC2VP7

Manufacturer Part Number
XC2VP7
Description
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Complete Data Sheet
Manufacturer
XILINX [Xilinx, Inc]
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XC2VP7 FF672
Manufacturer:
XILINX
0
Part Number:
XC2VP7 FF896 2C
Manufacturer:
XILINX
0
Part Number:
XC2VP7 FG456
Manufacturer:
XILINX
Quantity:
80
Part Number:
XC2VP7 FG456
Manufacturer:
XILINX
0
Part Number:
XC2VP7 FGG456
Quantity:
118
Part Number:
XC2VP7 FGG456
Manufacturer:
XILINX
0
Part Number:
XC2VP7-2FF672C
Manufacturer:
XILINX
0
Part Number:
XC2VP7-4FF896C
Manufacturer:
XILINX
Quantity:
280
Part Number:
XC2VP7-4FFG896C
Manufacturer:
XILINX
Quantity:
591
Part Number:
XC2VP7-4FFG896I
Manufacturer:
XILINX
Quantity:
648
Source-Synchronous Switching Characteristics
The parameters in this section provide the necessary values for calculating timing budgets for Virtex-II Pro
source-synchronous transmitter and receiver data-valid windows.
Table 61: Duty Cycle Distortion and Clock-Tree Skew
DS083 (v4.7) November 5, 2007
Product Specification
Notes:
1. These parameters represent the worst-case duty cycle distortion observable at the pins of the device using LVDS output buffers. For
2. This value represents the worst-case clock-tree skew observable between sequential I/O elements. Significantly less clock-tree skew
Duty Cycle Distortion
Clock Tree Skew
cases where other I/O standards are used, IBIS can be used to calculate any additional duty cycle distortion that might be caused by
asymmetrical rise/fall times.
T
used to provide the negative-edge clock to the DDR element in the I/O. Users must follow the implementation guidelines contained
in
T
in the I/O.
exists for I/O registers that are close to each other and fed by the same or adjacent clock-tree branches. Use the Xilinx FPGA_Editor
and Timing Analyzer tools to evaluate clock skew specific to your application.
DCD_LOCAL
DCD_CLK180
XAPP685
Description
R
applies to cases where the dedicated path from the DCM to the BUFG is bypassed and where local (IOB) inversion is
for these specifications to apply.
applies to cases where the CLK180 output of the DCM is used to provide the negative-edge clock to the DDR element
(2)
(1)
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
T
T
DCD_CLK180
DCD_LOCAL
Symbol
T
CKSKEW
www.xilinx.com
XC2VPX20
XC2VPX70
XC2VP100
XC2VP20
XC2VP30
XC2VP40
XC2VP50
XC2VP70
XC2VP2
XC2VP4
XC2VP7
Device
All
0.10
0.10
0.13
0.13
0.13
0.20
0.20
0.20
0.33
0.40
0.54
0.54
N/A
7
Speed Grade
0.10
0.11
0.13
0.13
0.13
0.21
0.21
0.22
0.34
0.41
0.59
0.59
0.79
6
0.20
0.13
0.13
0.13
0.13
0.22
0.22
0.24
0.35
0.42
0.64
0.64
0.87
5
Module 3 of 4
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
49

Related parts for XC2VP7