XCV405E-7BG556I XILINX [Xilinx, Inc], XCV405E-7BG556I Datasheet - Page 12

• Manufacturer Part Number: XCV405E-7BG556I
• Description: Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
• Manufacturer: XILINX [Xilinx, Inc]

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
DLL provides four quadrature phases of the source clock,
and can double the clock or divide the clock by 1.5, 2, 2.5, 3,
4, 5, 8, or 16.
The DLL also operates as a clock mirror. By driving the output
from a DLL off-chip and then back on again, the DLL can be
used to de-skew a board level clock among multiple devices.
In order to guarantee that the system clock is operating cor-
rectly prior to the FPGA starting up after configuration, the
DLL can delay the completion of the configuration process
until after it has achieved lock.
For more information about DLL functionality, see the
Design Consideration section of the data sheet.
Boundary Scan
Virtex-E devices support all the mandatory boundary-scan
instructions specified in the IEEE standard 1149.1. A Test
Access Port (TAP) and registers are provided that imple-
ment the EXTEST, INTEST, SAMPLE/PRELOAD, BYPASS,
IDCODE, USERCODE, and HIGHZ instructions. The TAP
also supports two internal scan chains and configura-
tion/readback of the device.
The JTAG input pins (TDI, TMS, TCK) do not have a V
requirement, and operate with either 2.5 V or 3.3 V input
signalling levels. The output pin (TDO) is sourced from the
V
levels, the bank should be supplied with 3.3 V.
Boundary-scan operation is independent of individual IOB
configurations, and unaffected by package type. All IOBs,
including un-bonded ones, are treated as independent
3-state bidirectional pins in a single scan chain. Retention of
Module 2 of 4
8
CCO
in bank 2, and for proper operation of LVTTL 3.3 V
www.xilinx.com
1-800-255-7778
CCO
the bidirectional test capability after configuration facilitates
the testing of external interconnections.
Table 6
Virtex-E FPGAs. Internal signals can be captured during
EXTEST by connecting them to un-bonded or unused IOBs.
They can also be connected to the unused outputs of IOBs
defined as unidirectional input pins.
Before the device is configured, all instructions except
USER1 and USER2 are available. After configuration, all
instructions are available. During configuration, it is recom-
mended that those operations using the boundary-scan
register (SAMPLE/PRELOAD, INTEST, EXTEST) not be
performed.
In addition to the test instructions outlined above, the
boundary-scan circuitry can be used to configure the
FPGA, and also to read back the configuration data.
lists the boundary-scan instructions supported in
Figure 10: DLL Locations
DLLDLL
DLLDLL
Primary DLLs
DLLDLL
DLLDLL
DS025-2 (v2.1) July 17, 2002
XCVE_0010
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