XCV405E-7BG556I XILINX [Xilinx, Inc], XCV405E-7BG556I Datasheet - Page 54

• Manufacturer Part Number: XCV405E-7BG556I
• Description: Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
• Manufacturer: XILINX [Xilinx, Inc]

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
Table 44:
Revision History
The following table shows the revision history for this document.
Virtex-E Extended Memory Data Sheet
The Virtex-E Extended Memory Data Sheet contains the following modules:
•
•
Module 2 of 4
50
IOBUFDS_LD_LVDS
IOBUFDS_LDE_LVDS
IOBUFDS_LDC_LVDS
IOBUFDS_LDCE_LVDS
IOBUFDS_LDP_LVDS
IOBUFDS_LDPE_LVDS
03/23/00
08/01/00
09/19/00
11/20/00
04/02/01
04/19/01
07/23/01
11/16/01
07/17/02
DS025-1, Virtex-E 1.8V Extended Memory FPGAs:
Introduction and Ordering Information (Module 1)
DS025-2, Virtex-E 1.8V Extended Memory FPGAs:
Functional Description (Module 2)
Date
Bidirectional I/O Library Macros (Continued)
Version
Name
1.0
1.1
1.2
1.3
1.4
1.5
1.6
2.0
2.1
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•
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Initial Xilinx release.
Accumulated edits and fixes. Upgrade to Preliminary. Preview -8 numbers added.
Reformatted to adhere to corporate documentation style guidelines. Minor changes in
BG560 pin-out table.
In Table 3 (Module 4), FG676 Fine-Pitch BGA — XCV405E, the following pins are no
longer labeled as VREF: B7, G16, G26, W26, AF20, AF8, Y1, H1.
Min values added to Virtex-E Electrical Characteristics tables.
Updated speed grade -8 numbers in Virtex-E Electrical Characteristics tables
(Module 3).
Updated minimums in Table 11 (Module 2), and added notes to Table 12 (Module 2).
Added to note 2 of Absolute Maximum Ratings (Module 3).
Changed all minimum hold times to –0.4 for Global Clock Set-Up and Hold for LVTTL
Standard, with DLL (Module 3).
Revised maximum T
In
and pin G16 is now labeled as VREF.
Updated values in
Converted data sheet to modularized format.
Modified
Made minor edits to text under Configuration.
Added warning under
bitstream causes configuration to fail and can damage the device.
Data sheet designation upgraded from Preliminary to Production.
Table
4, FG676 Fine-Pitch BGA — XCV405E, pin B19 is no longer labeled as VREF,
Figure
30, which shows “DLL Generation of 4x Clock in Virtex-E Devices.”
D, T, GE, G, CLR
D, T, GE, G, PRE
Virtex-E Switching Characteristics
www.xilinx.com
1-800-255-7778
D, T, G, PRE
D, T, G, CLR
DLLPW
D, T, GE, G
Configuration
Inputs
D, T, G
in -6 speed grade for DLL Timing Parameters (Module 3).
•
•
DS025-3, Virtex-E 1.8V Extended Memory FPGAs:
DC and Switching Characteristics (Module 3)
DS025-4, Virtex-E 1.8V Extended Memory FPGAs:
Pinout Tables (Module 4)
section that attempting to load an incorrect
Revision
Bidirectional
IO, IOB
IO, IOB
IO, IOB
IO, IOB
IO, IOB
IO, IOB
tables.
DS025-2 (v2.1) July 17, 2002
Outputs
Q
Q
Q
Q
Q
Q
R