MK61FN1M0VMD12 FREESCALE [Freescale Semiconductor, Inc], MK61FN1M0VMD12 Datasheet - Page 17

• Manufacturer Part Number: MK61FN1M0VMD12
• Description: K61 Sub-Family Data Sheet
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

5.2.4 Power mode transition operating behaviors
All specifications except t
assume this clock configuration:
1. Normal boot (FTFE_FOPT[LPBOOT]=1)
5.2.5 Power consumption operating behaviors
Freescale Semiconductor, Inc.
Symbol
I
I
Symbol
DD_RUN
DD_RUN
• CPU and system clocks = FEI 100 MHz
• Bus clock = 50 MHz
• FlexBus clock = 50 MHz
• Flash clock = 25 MHz
I
t
DDA
POR
Analog supply current
Run mode current — all peripheral clocks
disabled, code executing from flash
Run mode current — all peripheral clocks
enabled, code executing from flash
Description
After a POR event, amount of time from the point V
reaches 1.71 V to execution of the first instruction
across the operating temperature range of the chip.
Description
• @ 1.8V
• @ 3.0V
• @ 1.8V
• @ 3.0V
• VLLS1 → RUN
• VLLS2 → RUN
• VLLS3 → RUN
• LLS → RUN
• VLPS → RUN
• STOP → RUN
Table 5. Power mode transition operating behaviors
Table 6. Power consumption operating behaviors
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
POR
, and VLLSx→RUN recovery times in the following table
Table continues on the next page...
Preliminary
DD
Min.
—
—
—
—
—
Min.
—
—
—
—
—
—
—
Typ.
65
65
95
95
—
Max.
TBD
TBD
300
126
5.0
82
82
See note
Max.
TBD
TBD
TBD
TBD
Unit
μs
μs
μs
μs
μs
μs
μs
Unit
mA
mA
mA
mA
mA
Notes
Notes
General
1
1
2
3
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