MK61FN1M0VMD12 FREESCALE [Freescale Semiconductor, Inc], MK61FN1M0VMD12 Datasheet - Page 38
MK61FN1M0VMD12
Manufacturer Part Number
MK61FN1M0VMD12
Description
K61 Sub-Family Data Sheet
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
1.MK61FN1M0VMD12.pdf
(82 pages)
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Peripheral operating requirements and behaviors
6.4.3 NFC specifications
The NAND flash controller (NFC) implements the interface to standard NAND flash
memory devices. This section describes the timing parameters of the NFC.
In the following table:
which are defined as:
The SCALER value is derived from the fractional divider specified in the SIM's
CLKDIV4 register:
38
• T
• T
EZP_CK
EZP_CS
EZP_Q (output)
EZP_D (input)
Num
EP8
EP9
H
L
is flash clock low time,
is the flash clock high time and
EZP_CK low to EZP_Q output invalid (hold)
EZP_CS negation to EZP_Q tri-state
Description
Table 23. EzPort switching specifications (continued)
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
EP3
Figure 10. EzPort Timing Diagram
SCALER =
EP5
T
EP6
EP7
NFC
EP4
=
SIM_CLKDIV4[NFCFRAC] + 1
SIM_CLKDIV4[NFCDIV] + 1
T +
Preliminary
EP8
L
EP9
T
H
=
T
SCALER
input clock
EP2
Min.
—
0
Freescale Semiconductor, Inc.
Max.
12
—
Unit
ns
ns
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