CY8C20110_12 CYPRESS [Cypress Semiconductor], CY8C20110_12 Datasheet - Page 38

• Manufacturer Part Number: CY8C20110_12
• Manufacturer: CYPRESS [Cypress Semiconductor]

Glossary
Document Number: 001-54606 Rev. *G
interrupt
interrupt service
routine (ISR)
jitter
low-voltage
detect (LVD)
M8C
master device
microcontroller
mixed-signal
modulator
noise
oscillator
parity
Phase-locked
loop (PLL)
pinouts
port
Power on reset
(POR)
PSoC
®
(continued)
A suspension of a process, such as the execution of a computer program, caused by an event external to that
process, and performed in such a way that the process can be resumed.
A block of code that normal code execution is diverted to when the M8C receives a hardware interrupt. Many
interrupt sources may each exist with its own priority and individual ISR code block. Each ISR code block ends
with the RETI instruction, returning the device to the point in the program where it left normal program execution.
A circuit that senses V
An 8-bit Harvard-architecture microprocessor. The microprocessor coordinates all activity inside a PSoC by
interfacing to the Flash, SRAM, and register space.
A device that controls the timing for data exchanges between two devices. Or when devices are cascaded in
width, the master device is the one that controls the timing for data exchanges between the cascaded devices
and an external interface. The controlled device is called the slave device.
An integrated circuit chip that is designed primarily for control systems and products. In addition to a CPU, a
microcontroller typically includes memory, timing circuits, and I/O circuitry. The reason for this is to permit the
realization of a controller with a minimal quantity of chips, thus achieving maximal possible miniaturization. This
in turn, reduces the volume and the cost of the controller. The microcontroller is normally not used for
general-purpose computation as is a microprocessor.
The reference to a circuit containing both analog and digital techniques and components.
A device that imposes a signal on a carrier.
A circuit that may be crystal controlled and is used to generate a clock frequency.
A technique for testing transmitting data. Typically, a binary digit is added to the data to make the sum of all the
digits of the binary data either always even (even parity) or always odd (odd parity).
An electronic circuit that controls an oscillator so that it maintains a constant phase angle relative to a reference
signal.
The pin number assignment: the relation between the logical inputs and outputs of the PSoC device and their
physical counterparts in the printed circuit board (PCB) package. Pinouts involve pin numbers as a link between
schematic and PCB design (both being computer generated files) and may also involve pin names.
A group of pins, usually eight.
A circuit that forces the PSoC device to reset when the voltage is lower than a pre-set level. This is a type of
hardware reset.
Cypress Semiconductor’s PSoC
of Cypress.
1. A misplacement of the timing of a transition from its ideal position. A typical form of corruption that occurs on
2. The abrupt and unwanted variations of one or more signal characteristics, such as the interval between
1. A disturbance that affects a signal and that may distort the information carried by the signal.
2. The random variations of one or more characteristics of any entity such as voltage, current, or data.
serial data streams.
successive pulses, the amplitude of successive cycles, or the frequency or phase of successive cycles.
DD
and provides an interrupt to the system when V
®
is a registered trademark and Programmable System-on-Chip™ is a trademark
CY8C20160, CY8C20140
CY8C20110, CY8C20180
DD
falls lower than a selected threshold.
CY8C20142
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