CY8C20110_12 CYPRESS [Cypress Semiconductor], CY8C20110_12 Datasheet - Page 39

• Manufacturer Part Number: CY8C20110_12
• Manufacturer: CYPRESS [Cypress Semiconductor]

Glossary
Document Number: 001-54606 Rev. *G
PSoC Designer™ The software for Cypress’ Programmable System-on-Chip technology.
pulse width
modulator (PWM)
RAM
register
reset
ROM
serial
settling time
shift register
slave device
SRAM
SROM
stop bit
synchronous
tri-state
UART
user modules
user space
(continued)
An output in the form of duty cycle which varies as a function of the applied measurand
An acronym for random access memory. A data-storage device from which data can be read out and new data
can be written in.
A storage device with a specific capacity, such as a bit or byte.
A means of bringing a system back to a know state. See hardware reset and software reset.
An acronym for read only memory. A data-storage device from which data can be read out, but new data cannot
be written in.
The time it takes for an output signal or value to stabilize after the input has changed from one value to another.
A memory storage device that sequentially shifts a word either left or right to output a stream of serial data.
A device that allows another device to control the timing for data exchanges between two devices. Or when
devices are cascaded in width, the slave device is the one that allows another device to control the timing of data
exchanges between the cascaded devices and an external interface. The controlling device is called the master
device.
An acronym for static random access memory. A memory device where you can store and retrieve data at a high
rate of speed. The term static is used because, after a value is loaded into an SRAM cell, it remains unchanged
until it is explicitly altered or until power is removed from the device.
An acronym for supervisory read only memory. The SROM holds code that is used to boot the device, calibrate
circuitry, and perform Flash operations. The functions of the SROM may be accessed in normal user code,
operating from Flash.
A signal following a character or block that prepares the receiving device to receive the next character or block.
A function whose output can adopt three states: 0, 1, and Z (high-impedance). The function does not drive any
value in the Z state and, in many respects, may be considered to be disconnected from the rest of the circuit,
allowing another output to drive the same net.
A UART or universal asynchronous receiver-transmitter translates between parallel bits of data and serial bits.
Pre-build, pre-tested hardware/firmware peripheral functions that take care of managing and configuring the lower
level Analog and Digital PSoC Blocks. User Modules also provide high level API (Application Programming
Interface) for the peripheral function.
The bank 0 space of the register map. The registers in this bank are more likely to be modified during normal
program execution and not just during initialization. Registers in bank 1 are most likely to be modified only during
the initialization phase of the program.
1. Pertaining to a process in which all events occur one after the other.
2. Pertaining to the sequential or consecutive occurrence of two or more related activities in a single device or
1. A signal whose data is not acknowledged or acted upon until the next active edge of a clock signal.
2. A system whose operation is synchronized by a clock signal.
channel.
CY8C20160, CY8C20140
CY8C20110, CY8C20180
CY8C20142
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