CY8C20111_11 CYPRESS [Cypress Semiconductor], CY8C20111_11 Datasheet - Page 33

• Manufacturer Part Number: CY8C20111_11
• Manufacturer: CYPRESS [Cypress Semiconductor]

15. Examples of Frequently Used I
Document Number: 001-53516 Rev. *G
Note
10. The ‘W’ indicates the write transfer and the next byte of data represents the 7-bit I2C address. The I2C address is assumed to be ‘0’ in the above examples.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Sl. No.
Similarly ‘R’ indicates the read transfer followed by 7-bit address and data byte read operations.
Enter into setup mode
Enter into normal mode
Load factory defaults to RAM
registers
Do a software reset
Save current configuration to flash
Load factory defaults to RAM
registers and save as user configu-
ration
Disable combinational logic output to
DIG0
Disable combinational logic output to
DIG1
Clearing (logic 0) the both DIG0 and
DIG1 outputs
Setting (logic 1) the DIG0 and
clearing (Logic 0) the DIG1 outputs
Clearing (logic 0) the DIG0 and
Setting (Logic 1) the DIG1 outputs
Setting (logic 1) the both DIG0 and
DIG1 outputs
Change CapSense clock to IMO/2
Change value of IDAC0 to ‘x’h
Change value of IDAC1 to ‘y’h
Change value of IDAC0 and IDAC1
to ‘x’h and ‘y’h
Change the value FT0 to ‘x’h
Change the value FT1 to ‘y’h
Change the value FT0 and FT1 to ‘x’h
and ‘y’h
Change noise threshold to ‘x’h
Read CapSense button CS0 scan
results
Read CapSense button status
register
Requirement
W 00 A0 08
W 00 A0 07
W 00 A0 02
W 00 A0 08
W 00 A0 06
W 00 A0 01
W 00 A0 08
W 00 A0 02
W 00 A0 01
W 00 A0 06
W 00 1C 00
W 00 21 00
W 00 04 00
W 00 04 01
W 00 04 02
W 00 04 03
W 00 A0 08
W 00 51 20
W 00 A0 07
W 00 70 x
W 00 71 y
W 00 70 x y
W 00 66 x
W 00 67 y
W 00 66 x y
W 00 4E x
W 00 81 81
W 00 82
R 00 RD RD
RD RD
W 00 88
R 00 RD
2
C Commands
I
2
C Commands
RD RD
[10]
; Enter into setup mode
; Do software reset
; Enter into setup mode
; Load factory defaults to SRAM
; Save the configuration to flash. Wait for time specified in
Table
; Do software reset
Combinational logic output on DIG0 and DIG1 should be
disabled before dong this operation (SL# 7 and 8)
; Enter into setup mode
; CapSense clock is set as IMO/2
; Enter into normal mode
‘x’ represents new value of IDAC register
‘y’ represents new value of IDAC register
‘x’ and ‘y’ represents new value of IDAC register
‘x’ represents new value of FT register
‘y’ represents new value of FT register
‘x’ and ‘y’ represents new value of FT registers
; Select CapSense button for reading scan result
; Set the read point to 82h
; Consecutive 6 reads gets baseline, difference count and
raw count (all two byte each)
; Set the read pointer to 88
; Reading a byte gets status CapSense inputs
6.
CY8C20111, CY8C20121
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