XE8805 SEMTECH [Semtech Corporation], XE8805 Datasheet - Page 145

• Manufacturer Part Number: XE8805
• Description: Data Acquisition MCU
• Manufacturer: SEMTECH [Semtech Corporation]

When a value is written into the counter register while the counter is in counter mode, both the comparison value is
updated and the counter value is modified. In upcount mode, the register value is reset to zero. In downcount
mode, the comparison value is loaded into the counter. Due to the synchronization mechanism between the
processor clock domain and the external clock source domain, this modification of the counter value can be
postponed until the counter is enabled and it receives it’s first valid clock edge.
In the PWM mode, the counter value is not modified by the write operation in the counter register. Changing the
counter mode, does not update the counter value (no load in downcount mode).
20.7 Clock selection
The clock source for each counter can be individually selected by writing the appropriate value in the register
RegCntCtrlCk.
Table 20-10 gives the correspondence between the binary codes used for the configuration bits CntACkSel(1:0),
CntBCkSel(1:0), CntCCkSel(1:0) or CntDCkSel(1:0) and the clock source selected respectively for the counters
A, B, C or D.
The CkRc clock is the RC oscillator. The clocks below 32kHz can be derived from the RC oscillator or the crystal
oscillator (see the documentation of the clock block). A separate external clock source can be delivered on Port A
for each individual counter.
The external clock sources can be debounced or not by setting the Port A configuration registers.
The clock source can be changed only when the counter is stopped.
20.8 Counter mode selection
Each counter can work in one of the following modes:
The counters A and B or C and D can be cascaded or not. In cascaded mode, A and C are the LSB counters while
B and D are the MSB counters.
Table 20-11 shows the different operation modes of the counters A and B as a function of the mode control bits.
For all counter modes, the source of the down or upcount selection is given (either the bit CntADownUp or the bit
CntBDownUp). Also, the mapping of the interrupt sources IrqA and IrqB and the PWM output on PB(0) in these
different modes is shown.
© Semtech 2006
2) For slow operating counters (typically at least 8 times slower than the CPU clock), oversample the counter
3) Use the capture mechanism.
1) Counter, downcount & upcount
2) Captured counter, downcount & upcount (only counters A&B)
3) PWM, downcount
content and perform a majority operation on the consecutive read results to select the correct actual
content of the counter.
CntXCkSel(1:0)
11
10
01
00
Table 20-10: Clock sources for counters A, B, C and D
CounterA
PA(0)
CkRc/4
CkRc
CounterB
20-5
PA(1)
Clock source for
Ck128
CounterC
PA(2)
Ck32k
Ck1k
CounterD
PA(3)
XE8805/05A
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