XE8805 SEMTECH [Semtech Corporation], XE8805 Datasheet - Page 84

• Manufacturer Part Number: XE8805
• Description: Data Acquisition MCU
• Manufacturer: SEMTECH [Semtech Corporation]

15.4 Interrupts map
15.5 Conditional edge detection 1
Condition 1 is satisfied when S0=1 at the falling edge of S1. The bit UsrtCond1 in RegUsrtCond1 is set when the
condition 1 is detected and the USRT interface is enabled (UsrtEnable=1). Condition 1 is asserted for both modes
(receiver and transmitter). The UsrtCond1 bit is read only and is cleared by all reset conditions and by writing any
data to its address.
Condition 1 occurrence also generates an interrupt on Irq_cond1.
15.6 Conditional edge detection 2
© Semtech 2006
7-1
0
pos.
-
UsrtEdgeS0
RegUsrtEdgeS0
S1
S0
S1
S0
Irq_cond1
Irq_cond2
interrupt
source
r
r
rw
0000000
0 resetsystem
Table 15-7: RegUsrtEdgeS0
Table 15-8: Interrupts map
RegIrqMid(7)
RegIrqMid(6)
Figure 15-1: Condition 1
Figure 15-2: Condition 2
default mapping in the interrupt manager
reset
15-4
Unused
State
(1=detected).
RegUsrtBufferS1
of
rising
Cleared
function
edge
detection
by
XE8805/05A
on
reading
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S0