CP3UB17G38 NSC [National Semiconductor], CP3UB17G38 Datasheet - Page 102

• Manufacturer Part Number: CP3UB17G38
• Description: CP3UB17 Reprogrammable Connectivity Processor with USB Interface
• Manufacturer: NSC [National Semiconductor]

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If the module is only used for PCM conversions, the CVSD
clock can be disabled by clearing the CVSD Clock Enable
bit (CLKEN) in the control register.
17.3
The PCM2CVSD converter module transforms either 8-bit
logarithmic or 13- to 16-bit linear PCM samples at a fixed
rate of 8 ksps. The CVSD to PCM conversion format must
be specified by the CVSDCONV control bits in the CVSD
Control register (CVCTRL).
The CVSD algorithm is tuned for 13- or 14-bit right-aligned
data. It will operate with 16-bit data, but this will produce dis-
tortion. This can be handled by using the RESOLUTION
control bits in the CVSD Control register (CVCTRL) to spec-
ify shifting the data by 1, 2, or 3 bit positions before perform-
ing the conversion.
For linear PCM data, the resolution (13-, 14-, 15-, or 16-bit)
should be specified by the RESOLUTION bits for the reso-
lution of the linear data format. For maximum resolution with
A-Law log PCM data, the RESOLUTION bits should be pro-
grammed for 13-bit resolution. For µ-Law log PCM data, the
RESOLUTION bits should be programmed for 14-bit resolu-
tion.
If the resolution is not set properly, the audio signal may be
clipped or have reduced attenuation.
17.4
The converter core reads out the double-buffered PCMIN
register every 125 µs and writes a new 16-bit CVSD data
stream into the CVSD Out FIFO every 250 µs. If the PCMIN
buffer has not been updated with a new PCM sample be-
tween two reads from the CVSD core, the old PCM data is
used again to maintain a fixed conversion rate. Once a new
16-bit CVSD data stream has been calculated, it is copied
into the 8 × 16-bit wide CVSD Out FIFO.
If there are only three empty words (16-bit) left in the FIFO,
the nearly full bit (CVNF) is set, and, if enabled
(CVSDINT = 1), an interrupt request is asserted.
If the CVSD Out FIFO is full, the full bit (CVF) is set, and, if
enabled (CVSDERRINT = 1), an interrupt request is assert-
ed. In this case, the CVSD Out FIFO remains unchanged.
Within the interrupt handler, the CPU can read out the new
CVSD data. If the CPU reads from an already empty CVSD
Out FIFO, the FIFO automatically returns a checkerboard
pattern to guarantee a minimum level of distortion of the au-
dio stream.
17.5
The converter core reads from the CVSD In FIFO every
250 µs and writes a new PCM sample into the PCMOUT
buffer every 125 µs. If the previous PCM data has not yet
been transferred to the audio interface, it will be overwritten
with the new PCM sample.
If there are only three unread words left, the CVSD In Nearly
Empty bit (CVNE) is set and, if enabled (CVSDINT = 1), an
interrupt request is generated.
If the CVSD In FIFO is empty, the CVSD In Empty bit (CVE)
is set and, if enabled (CVSDERRINT = 1), an interrupt re-
quest is generated. If the converter core reads from an al-
CVSD CONVERSION
PCM TO CVSD CONVERSION
CVSD TO PCM CONVERSION
102
ready empty CVSD In FIFO, the FIFO automatically returns
a checkerboard pattern to guarantee a minimum level of dis-
tortion of the audio stream.
17.6
An interrupt is generated in any of the following cases:
Both the CVSD In and CVSD Out FIFOs have a size of
8 × 16 bit (8 words). The warning limits for the two FIFOs is
set at 5 words. (The CVSD In FIFO interrupt will occur when
there are 3 words left in the FIFO, and the CVSD Out FIFO
interrupt will occur when there are 3 or less empty words left
in the FIFO.) The limit is set to 5 words because Bluetooth
audio data is transferred in packages composed of 10 or
multiples of 10 bytes.
17.7
The CVSD module can operate with any of four DMA chan-
nels. Four DMA channels are required for processor inde-
pendent operation. Both receive and transmit for CVSD
data and PCM data can be enabled individually. The
PCM2CVSD module asserts a DMA request to the on-chip
DMA controller under the following conditions:
The CVSD/PCM module only supports indirect DMA trans-
fers. Therefore, transferring PCM data between the CVSD/
PCM module and another on-chip module requires two bus
cycles.
When a new PCM sample has been written into the
PCMOUT register and the CVCTRL.PCMINT bit is set.
When a new PCM sample has been read from the
PCMIN register and the CVCTRL.PCMINT bit is set.
When
(CVSTAT.CVNE = 1) and the CVCTRL.CVSDINT bit is
set.
When
(CVSTAT.CVNF = 1) and the CVCTRL.CVSDINT bit is
set.
When the CVSD In FIFO is empty (CVSTAT.CVE = 1)
and the CVCTRL.CVSDERRINT bit is set.
When the CVSD Out FIFO is full (CVSTAT.CVF = 1) and
the CVCTRL.CVSDERRINT bit is set.
The DMAPO bit is set and the PCMOUT register is full,
because it has been updated by the converter core with
a new PCM sample. (The DMA controller can read out
one PCM data word from the PCMOUT register.)
The DMAPI bit is set and the PCMIN register is empty,
because it has been read by the converter core. (The
DMA controller can write one new PCM data word into
the PCMIN register.)
The DMACO bit is set and a new 16-bit CVSD data
stream has been copied into the CVSD Out FIFO. (The
DMA controller can read out one 16-bit CVSD data word
from the CVSD Out FIFO.)
The DMACI bit is set and a 16-bit CVSD data stream has
been read from the CVSD In FIFO. (The DMA controller
can write one new 16-bit CVSD data word into the CVSD
In FIFO.)
INTERRUPT GENERATION
DMA SUPPORT
the
the
CVSD
CVSD
In
Out
FIFO
FIFO
is
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nearly
nearly
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