CP3UB17G38 NSC [National Semiconductor], CP3UB17G38 Datasheet - Page 38
CP3UB17G38
Manufacturer Part Number
CP3UB17G38
Description
CP3UB17 Reprogrammable Connectivity Processor with USB Interface
Manufacturer
NSC [National Semiconductor]
Datasheet
1.CP3UB17G38.pdf
(200 pages)
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8.5.10
The FMTRAN/FMSTRAN register is a byte-wide read/write
register that controls some program/erase transition times.
Software must not modify this register while program/erase
operation is in progress (FMBUSY set). At reset, this regis-
ter is initialized to 30h if the flash memory is idle. The CPU
bus master has read/write access to this register.
FTTRAN
8.5.11
The FMPROG/FSMPROG register is a byte-wide read/write
register that controls the programming pulse width. Soft-
ware must not modify this register while a program/erase
operation is in progress (FMBUSY set). At reset, this regis-
ter is initialized to 16h if the flash memory is idle. The CPU
bus master has read/write access to this register.
FTPROG
8.5.12
The FMPERASE/FSMPERASE register is a byte-wide
read/write register that controls the page erase pulse width.
Software must not modify this register while a program/
erase operation is in progress (FMBUSY set). At reset, this
register is initialized to 04h if the flash memory is idle. The
CPU bus master has read/write access to this register.
FTPER
7
7
7
Register (FMTRAN/FSMTRAN)
Register (FMPROG/FSMPROG)
Register (FMPERASE/FSMPERASE)
Flash Memory Transition Time Reload
Flash Memory Programming Time Reload
Flash Memory Page Erase Time Reload
The Flash TIming Transition Count field spec-
ifies a delay of (FTTRAN + 1) prescaler output
clocks.
The Flash Timing Programming Pulse Width
field specifies a programming pulse width of
8 × (FTPROG + 1) prescaler output clocks.
The Flash Timing Page Erase Pulse Width
field specifies a page erase pulse width of
4096 × (FTPER + 1) prescaler output clocks.
FTPROG
FTTRAN
FTPER
0
0
0
38
8.5.13
The FMMERASE0/FSMMERASE0 register is a byte-wide
read/write register that controls the module erase pulse
width. Software must not modify this register while a pro-
gram/erase operation is in progress (FMBUSY set). At re-
set, this register is initialized to EAh if the flash memory is
idle. The CPU bus master has read/write access to this reg-
ister.
FTMER
8.5.14
The FMEND/FSMEND register is a byte-wide read/write
register that controls the delay time after a program/erase
operation. Software must not modify this register while a
program/erase operation is in progress (FMBUSY set). At
reset, this register is initialized to 18h when the flash mem-
ory on the chip is idle. The CPU bus master has read/write
access to this register.
FTEND
8.5.15
The FMMEND/FSMMEND register is a byte-wide read/write
register that controls the delay time after a module erase op-
eration. Software must not modify this register while a pro-
gram/erase operation is in progress (FMBUSY set). At
reset, this register is initialized to 3Ch if the flash memory is
idle. The CPU bus master has read/write access to this reg-
ister.
FTMEND
7
7
7
Flash Memory Module Erase Time Reload
Register 0 (FMMERASE0/FSMMERASE0)
Flash Memory End Time Reload Register
(FMEND/FSMEND)
Flash Memory Module Erase End Time Reload
Register (FMMEND/FSMMEND)
The Flash Timing Module Erase Pulse Width
field specifies a module erase pulse width of
4096 × (FTMER + 1) prescaler output clocks.
The Flash Timing End Delay Count field spec-
ifies a delay of (FTEND + 1) prescaler output
clocks.
The Flash Timing Module Erase End Delay
Count field specifies a delay of 8 × (FTMEND
+ 1) prescaler output clocks.
FTMEND
FTMER
FTEND
0
0
0
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