MPC8270 MOTOROLA [Motorola, Inc], MPC8270 Datasheet - Page 22

• Manufacturer Part Number: MPC8270
• Description: PowerQUICC II Family Hardware Specifications
• Manufacturer: MOTOROLA [Motorola, Inc]

Figure 10 shows signal behavior for all parity modes (including ECC, RMW parity, and standard parity).
Figure 11 shows signal behavior in MEMC mode.
22
DATA bus, ECC, and PARITY mode
DATA bus, ECC, and PARITY mode
Memory controller signals
DP mode output signal
DP mode input signal
DP mode input signal
Generally, all MPC8280 bus and system output signals are driven from the
rising edge of the input clock (CLKin). Memory controller signals,
however, trigger on four points within a CLKin cycle. Each cycle is
divided by four internal ticks: T1, T2, T3, and T4. T1 always occurs at the
rising edge, and T3 at the falling edge, of CLKin. However, the spacing of
T2 and T4 depends on the PLL clock ratio selected, as shown in Table 13.
Pipeline mode—
Pipeline mode—
MPC8280 PowerQUICC II™ Family Hardware Specifications
input signals
input signals
CLKin
V_CLK
CLKin
Figure 11. MEMC Mode Diagram
Figure 10. Parity Mode Diagram
sp33b
NOTE
sp14a
sp13a
sp34/sp30
sp14
sp13
sp10
sp10
sp10
sp10
sp30
MOTOROLA