PIC12F1516 MICROCHIP [Microchip Technology], PIC12F1516 Datasheet - Page 80

• Manufacturer Part Number: PIC12F1516
• Description: 28/40/44-Pin Flash Microcontrollers with nanoWatt XLP Technology
• Manufacturer: MICROCHIP [Microchip Technology]

PIC16(L)F1516/7/8/9
7.6
7.6.1
The INTCON register is a readable and writable
register, which contains the various enable and flag bits
for TMR0 register overflow, interrupt-on-change and
external INT pin interrupts.
REGISTER 7-1:
DS41452B-page 80
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
R/W-0/0
GIE
Interrupt Control Registers
The IOCIF Flag bit is read-only and cleared when all the Interrupt-on-Change flags in the IOCBF register
have been cleared by software.
INTCON REGISTER
GIE: Global Interrupt Enable bit
1 = Enables all active interrupts
0 = Disables all interrupts
PEIE: Peripheral Interrupt Enable bit
1 = Enables all active peripheral interrupts
0 = Disables all peripheral interrupts
TMR0IE: Timer0 Overflow Interrupt Enable bit
1 = Enables the Timer0 interrupt
0 = Disables the Timer0 interrupt
INTE: INT External Interrupt Enable bit
1 = Enables the INT external interrupt
0 = Disables the INT external interrupt
IOCIE: Interrupt-on-Change Interrupt Enable bit
1 = Enables the interrupt-on-change interrupt
0 = Disables the interrupt-on-change interrupt
TMR0IF: Timer0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed
0 = TMR0 register did not overflow
INTF: INT External Interrupt Flag bit
1 = The INT external interrupt occurred
0 = The INT external interrupt did not occur
IOCIF: Interrupt-on-Change Interrupt Flag bit
1 = When at least one of the interrupt-on-change pins changed state
0 = None of the interrupt-on-change pins have changed state
R/W-0/0
PEIE
INTCON: INTERRUPT CONTROL REGISTER
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
R/W-0/0
TMR0IE
R/W-0/0
INTE
Preliminary
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
(1)
R/W-0/0
IOCIE
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE, of the INTCON register.
User software should ensure the appropri-
ate interrupt flag bits are clear prior to
enabling an interrupt.
R/W-0/0
TMR0IF
 2011 Microchip Technology Inc.
R/W-0/0
INTF
IOCIF
R-0/0
bit 0