DP83256VF-AP NSC [National Semiconductor], DP83256VF-AP Datasheet - Page 25

• Manufacturer Part Number: DP83256VF-AP
• Manufacturer: NSC [National Semiconductor]

3 0 Functional Description
If the TCO Mask (TCOM) bit of the CMTCMR is set then
whenever the CMTCR TCO bit becomes set the Receive
Condition
(RCRB CSE) bit will be set This allows an interrupt to be
generated for the trigger event
As an example suppose the PCM state machine is in the
ACTIVE state From this state if a Halt Line State (HLS) or
Quiet Line State (QLS) is detected or the Noise Threshold
is reached the state machine must move to the PC Break
state and begin transmitting QLS To implement this behav-
ior
TDR TTM2–0 to 110 (Quiet Transmit) set TDR TOHLS
TDR TOQLS and TDR TONT and reset all other bits (TO-
SILS and TOMLS) Also set CMTCMR TCOM if an interrupt
is desired
CF REACT
CF React is one of the timing restrictions imposed by Con-
nection Management (CMT) It is one of the two most crit-
ical
PC React)
The ANSI SMT standard states that ‘‘CF React is the max-
imum time for CFM Configuration Management to recon-
figure to remove a non-Active connection from the token
path ’’
The range for the timer is CF React
default value equal to 3 0 ms
The PLAYER
uration Register and a set of CMT Condition Registers that
can be used to satisfy the CF React timing
he Trigger Transition Configuration Register (TTCR) holds
the new configuration switch settings to be loaded into the
Configuration Register (CR) when a trigger condition occurs
Enabling line state triggering with the Trigger Definition Reg-
ister (TDR) bits 3–7 also enables the CF React response
This means that whenever trigger conditions are actively
used for PC React the value of the TTCR register will be
used also This implies that it either must always then be
loaded with the current configuration setting causing no
change to the CR or it must be loaded with the appropriate
value to accommodate the CF React function
The Trigger Transition Configuration Register (TTCR) must
be set the configuration desired when the trigger condition
occurs When the trigger condition occurs the value of this
register is loaded into the Configuration Register (CR) Dur-
ing this time writes to the CR are inhibited
To continue the example from the PC React description
suppose that when in the ACTIVE state for the PCM state
machine the CFM state machine is also in the THRU A
state
CMTCMR TCOM bit and it is desired to not implement CF
React TTCR must be set to the present value of CR If it is
desired to not implement CF React then TTCR should be
set to the value which would change the configuration to the
WRAP state The wrap conditions WRAP A or WRAP B
depend on which PHY gets reconfigured
when
timing
If
Register
trigger
the
a
restrictions
device contains a Trigger Transition Config-
PC ACTIVE
conditions
B’s
imposed
Connection
state
are
s
(the
enabled
is
3 0 ms and has a
Service
(Continued)
entered
other
via
Event
being
the
set
25
AUTO SCRUBBING
Auto Scrubbing is an additional CMT feature that further
enhances the automatic configuration switch setting in or-
der to meet the CF React timing When enabled Auto
Scrubbing causes 2 PHY Invalid symbols followed by
Scrub Symbol pairs (Idles) to be sourced for a user select-
able duration (the scrubbing time) after a trigger condition
(the same one used for PC React and CF React) occurs
and prior to a change in the configuration switch setting on
all indicate ports that will be changed
Auto Scrubbing is enabled by setting the Enable Scrubbing
on Trigger Conditions (ESTC) bit of Mode Register 2
(MODE2)
The Scrub Timer Threshold Register (STTR) defines the du-
ration of the scrubbing which can last up to approximately
10ms The Scrub Timer Value Register (STVR) can be used
to examine a snapshot of the upper 8 bits of the STTR
register
TIMER IDLE DETECTION
The Idle Detection Timer is required to flag the continued
presence of the Idle Line State for a duration of 8 Idle Sym-
bol pairs plus 1 symbol pair
This feature is implemented in the Receiver Block by the
Super Idle Line State (SILS)
NOISE EVENT COUNTER
The Noise Event Counter can be used to time the duration
between Noise Events (which are described in detail below)
and to count frame sizes The first feature is the most often
recognized but the second is often overlooked and can
lead to potential difficulty if not properly set
The Noise Event Counter is implemented as a pair of down
counters one the actual Noise Counter and the other a
Noise Counter Prescaling value The Noise Threshold Reg-
ister (NTR) and the Noise Prescale Threshold Register
(NPTR) can be programmed to the counter’s initial value
while the Current Noise Count Register (CNCR) and the
Current Noise Prescale Count Register (CNPCR) provide a
snapshot of the actual counter
The Noise Event Counter decrements whenever a Noise
Line State (NLS) Line State Unknown (LSU) or Active Line
State (ALS) is received and has its start value reloaded
whenever it receives Halt Line State (HLS) Idle Line State
(ILS) Master Line State (MLS) Quiet Line State (QLS) or
No Signal Detect (NSD) The Noise Event Counter is also
reset for a Start or End Delimiter This means the Noise
counter increments for bad events as well as for every data
symbol in a frame Should the Noise Counter expire it indi-
cates that a new line state (including ALS) has not been
entered for NT MAX time This indicates that either a
frame is too long or that noise is being received
For this reason it is important to choose a value for the
counter that is larger than the longest frame of 4500 bytes
The ANSI SMT specification recommends a value for
NT MAX of 1 3ms for the noise threshold
A Noise Event is defined as follows
A noise event is a noisebyte or a byte of data which is not in
line with the current line state indicating error or corruption