DP83256VF-AP NSC [National Semiconductor], DP83256VF-AP Datasheet - Page 57

• Manufacturer Part Number: DP83256VF-AP
• Manufacturer: NSC [National Semiconductor]

Bit
D0
D1
D2
D3
D4
D5
D6
D7
5 0 Registers
5 13 RECEIVE CONDITION MASK REGISTER B (RCMRB)
The Receive Condition Mask Register B allows the user to dynamically select which events will generate an interrupt
The Receive Condition B bit (RCB) of the Interrupt Condition Register (ICR) will be set to 1 when one or more bits within the
Receive Condition Register B (RCRA) is set to 1 and the corresponding mask bits in this register is also set to 1
Since this register is cleared (i e set to 0) during the reset process all interrupts are initially masked
ACCESS RULES
RESM
ILSM
STM
ALSM
LSUPVM
CSEM
EBOUM
SILSM
RESM
Symbol
D7
ADDRESS
0Ch
SILSM
IDLE LINE STATE MASK The mask bit for the Idle Line State bit (ILS) of the Receive Condition Register B
(RCRB)
STATE THRESHOLD MASK The mask bit for the State Threshold bit (ST) of the Receive Condition Register B
(RCRB)
ACTIVE LINE STATE MASK The mask bit for the Active Line State bit (ALS) of the Receive Condition Register
B (RCRB)
LINE STATE UNKNOWN AND PHY VALID MASK The mask bit for the Line State Unknown and PHY Valid bit
(LSUPV) of the Receive Condition Register B (RCRB)
CASCADE SYNCHRONIZATION ERROR MASK CONNECTION SERVICE EVENT MASK
The mask bit for the Cascade Synchronization Error Connection service event bit (CSE) of the Receive Condition
Register B (RCRB)
ELASTICITY BUFFER OVERFLOW UNDERFLOW MASK The mask bit for the Elasticity Buffer Overflow
Underflow bit (EBOU) of the Receive Condition Register B (RCRB)
SUPER IDLE LINE STATE MASK The mask bit for the Super Idle Line State bit (SILS) of the Receive Condition
Register B (RCRB)
RESERVED MASK The mask bit for the Reserved bit (RES) of the Receive Condition Register B (RCRB)
D6
(Continued)
Always
READ
EBOUM
D5
CSEM
D4
WRITE
Always
LSUPVM
D3
57
Description
ALSM
D2
STM
D1
ILSM
D0