MC68HC08AZ60CFU MOTOROLA [Motorola, Inc], MC68HC08AZ60CFU Datasheet - Page 99

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MC68HC08AZ60CFU

Manufacturer Part Number
MC68HC08AZ60CFU
Description
Advance Information
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
17-sim
MOTOROLA
break status register (SBSR). If the COP disable bit, COPD, in the
configuration register is logic 0, then the computer operating properly
module (COP) is enabled and remains active in wait mode.
EXITSTOPWAIT
NOTE: EXITSTOPWAIT =
CGMXCLK
R/W
Freescale Semiconductor, Inc.
IDB
IAB
NOTE: Previous data can be operand data or the WAIT opcode, depending on the last instruction.
IDB
IAB
For More Information On This Product,
IDB
RST
IAB
$A6
Figure 13. Wait Recovery from Interrupt or Break
WAIT ADDR
System Integration Module (SIM)
$A6
Figure 14. Wait Recovery from Internal Reset
Go to: www.freescale.com
$6E0B
$A6
PREVIOUS DATA
$6E0B
$A6
Figure 12. Wait Mode Entry Timing
RST
$A6
WAIT ADDR + 1
$A6
pin OR CPU interrupt OR break interrupt
$6E0C
$01
Cycles
32
NEXT OPCODE
$00FF
$0B
Cycles
32
SAME
$00FE
System Integration Module (SIM)
$6E
SAME
MC68HC08AZ60 — Rev 1.0
$00FD
RST VCT H
SAME
Low-Power Modes
$00FC
RST VCT L
SAME
99

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