DP83936AVF NSC [National Semiconductor], DP83936AVF Datasheet - Page 65

• Manufacturer Part Number: DP83936AVF
• Description: Full Duplex SONICTM-T Systems-Oriented Network Interface Controller with Twisted Pair Interface
• Manufacturer: NSC [National Semiconductor]

7 0 Bus Interface
7 3 5 4 Memory Cycle for BMODE
Synchronous Mode
On the rising edge of T1 the SONIC-T asserts ADS and
ECS to indicate that the memory cycle is starting The ad-
dress (A31–A1) bus status (S2–S0) and the direction
strobe (MWR) are driven and do not change for the remain-
der of the memory cycle On the falling edge of T1 the
SONIC-T deasserts ECS ADS is deasserted on the rising
edge of T2
FIGURE 7-13 Memory Write BMODE
FIGURE 7-12 Memory Read BMODE
(Continued)
e
0
65
e
e
7-13) data is driven on the falling edge of T1 and stays
In Synchronous mode RDYi is sampled on the rising edge
at the end of T2 (the rising edge of the next T1) T2 states
will be repeated until RDYi is sampled properly In a low
state RDYi must meet the setup and hold times with respect
to the rising edge of bus clock for proper operation
During read cycles (Figure 7-12) data (D31– D0) is latched
at the rising edge at the end of T2 For write cycles (Figure
driven until the end of the cycle
0 Synchronous (1 Wait-State)
0 Synchronous (1 Wait-State)
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