DP83936AVF NSC [National Semiconductor], DP83936AVF Datasheet - Page 81

• Manufacturer Part Number: DP83936AVF
• Description: Full Duplex SONICTM-T Systems-Oriented Network Interface Controller with Twisted Pair Interface
• Manufacturer: NSC [National Semiconductor]

Number
T9
T11
T11b
T11d
T12
T12b
T12d
T15
T18
T32a
T33a
T36
T37
T39
9 0 AC and DC Specifications
MEMORY WRITE BMODE
Note 1 For successive read operations MWR remains high
Note 2 DS will only be asserted if the bus cycle has at least one wait state inserted
Note 3 This setup time assures that the SONIC-T terminates the memory cycle on the next bus clock (BSCK) RDYi does not need to be synchronized to the bus
clock though since it is an asynchronous input in this case RDYi is sampled during the falling edge of BSCK If the SONIC-T samples RDYi low during the T1
cycle the SONIC-T will finish the current access in a total of two bus clocks instead of three which would be the case if RDYi had been sampled low during
T2 (wait) (This is assuming that programmable wait states are set to 0 )
Note 4 One idle clock cycle (Ti) will be inserted between the last write cycle and the following read cycle in RDA and TDA operation Note that the data bus will
become TRI-STATE from the rising edge of the clock after the idle cycle (see T52 for BSCK to data TRI-STATE timing)
BSCK to Address Valid Hold Time
BSCK to ADS Low
BSCK to ECS Low
BSCK to DS Low
BSCK to ADS High
BSCK to ECS High
BSCK to DS High
ADS High Width
Write Data Strobe Low Width (Note 2)
RDYi Asynchronous Setup to BSCK (Note 3)
RDYi Asynchronous Hold from BSCK
BSCK to Memory Write Data Valid Hold Time
(Note 4)
BSCK to MWR (Write) Valid (Note 1)
Write Data Valid to DS Low
e
0 ASYNCHRONOUS MODE
Parameter
(Continued)
81
Min
45
40
34
3
5
5
3
20 MHz
Max
26
19
17
24
29
17
26
50
24
Min
35
21
30
3
4
5
3
25 MHz
Max
24
17
15
22
27
15
48
22
24
Min
25
20
3
3
5
3
7
33 MHz
TL F 12597– 62
http
Max
22
15
13
20
25
13
46
20
22
www national com
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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