PIC18F2423 MICROCHIP [Microchip Technology], PIC18F2423 Datasheet - Page 283
![no-image](/images/no-image-200.jpg)
PIC18F2423
Manufacturer Part Number
PIC18F2423
Description
28/40/44-Pin, Enhanced Flash Microcontrollers with 12-Bit A/D and nanoWatt Technology
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet
1.PIC18F2423.pdf
(392 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F2423-I/SP
Manufacturer:
MICROCHIP
Quantity:
1 290
Part Number:
PIC18F2423-I/SP
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- Current page: 283 of 392
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BNC
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
© 2007 Microchip Technology Inc.
Q Cycle Activity:
If Jump:
If No Jump:
Before Instruction
After Instruction
operation
Decode
Decode
PC
If Carry
If Carry
Q1
No
Q1
PC
PC
Read literal
Read literal
operation
Branch if Not Carry
BNC
-128 ≤ n ≤ 127
if Carry bit is ‘0’
(PC) + 2 + 2n → PC
None
If the Carry bit is ‘0’, then the program
will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
1
1(2)
HERE
1110
Q2
No
Q2
‘n’
‘n’
=
=
=
=
=
n
address (HERE)
0;
address (Jump)
1;
address (HERE + 2)
0011
BNC
operation
Process
Process
Data
Data
Q3
No
Q3
Jump
nnnn
Write to PC
operation
operation
PIC18F2423/2523/4423/4523
Q4
Q4
No
No
nnnn
Preliminary
BNN
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
If Jump:
If No Jump:
Before Instruction
After Instruction
operation
Decode
Decode
PC
If Negative
If Negative
Q1
No
Q1
PC
PC
Read literal
Read literal
operation
Branch if Not Negative
BNN
-128 ≤ n ≤ 127
if Negative bit is ‘0’
(PC) + 2 + 2n → PC
None
If the Negative bit is ‘0’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
1
1(2)
HERE
1110
Q2
Q2
No
‘n’
‘n’
=
=
=
=
=
n
address (HERE)
0;
address (Jump)
1;
address (HERE + 2)
0111
BNN
operation
Process
Process
Data
Data
Q3
No
Q3
DS39755B-page 281
Jump
nnnn
Write to PC
operation
operation
Q4
Q4
No
No
nnnn
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