MC68HC705JD FREESCALE [Freescale Semiconductor, Inc], MC68HC705JD Datasheet - Page 25

• Manufacturer Part Number: MC68HC705JD
• Description: member of the low-cost
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

4.1.4 Program Counter
4.1.5 Condition Code Register
4.1.5.1 Half-Carry Flag
4.1.5.2 Interrupt Mask
4.1.5.3 Negative Flag
Rev. 2
The program counter is a 16-bit register that contains the address of the next
instruction or operand to be fetched. The four most significant bits of the program
counter are permanently fixed at 0000. In MC68HC05J1 emulation mode, the five
most significant bits are fixed at 00000.
Normally, the address in the program counter automatically increments to the next
sequential memory location every time an instruction or operand is fetched. Jump,
branch, and interrupt operations load the program counter with an address other than
that of the next sequential location.
The condition code register is an 8-bit register whose three most significant bits are
permanently fixed at 111. The condition code register contains the interrupt mask
and four flags that indicate the results of the instruction just executed. The following
paragraphs describe the functions of the condition code register.
The CPU sets the half-carry flag when a carry occurs between bits 3 and 4 of the
accumulator during an ADD or ADC operation. The half-carry flag is required for
binary-coded decimal (BCD) arithmetic operations.
Setting the interrupt mask disables interrupts. If an interrupt request occurs while the
interrupt mask is zero, the CPU saves the CPU registers on the stack, sets the
interrupt mask, and then fetches the interrupt vector. If an interrupt request occurs
while the interrupt mask is set, the interrupt request is latched. Normally, the CPU
processes the latched interrupt as soon as the interrupt mask is cleared again.
A return from interrupt (RTI) instruction pulls the CPU registers from the stack,
restoring the interrupt mask to its cleared state. After any reset, the interrupt mask is
set and can be cleared only by a software instruction.
The CPU sets the negative flag when an arithmetic operation, logical operation, or
data manipulation produces a negative result. Bit 7 of the negative result is
automatically set, so the negative flag can be used to check an often-tested bit by
assigning it to bit 7 of a register or memory location. Loading the accumulator with
the contents of that register or location then sets or clears the negative flag according
to the state of the tested bit.
Freescale Semiconductor, Inc.
For More Information On This Product,
CENTRAL PROCESSOR UNIT
Go to: www.freescale.com
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