MC68HC705JD FREESCALE [Freescale Semiconductor, Inc], MC68HC705JD Datasheet - Page 32

• Manufacturer Part Number: MC68HC705JD
• Description: member of the low-cost
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

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5.1.2 External Reset
5.1.3 Computer Operating Properly (COP) Reset
5.1.4 Illegal Address Reset
5-2
COPR — COP Control Register
RESET
A 4064 t
the clock generator to stabilize. If the RESET pin is at a logical zero at the end of
4064 t
goes to a logical one.
A zero applied to the RESET pin for one and one-half t
reset. A Schmitt trigger senses the logic level at the RESET pin.
A timeout of the COP timer generates a COP reset. The COP timer is part of a
software error detection system and must be cleared periodically to start a new
timeout period. (See
reset, write a zero to bit 0 (COPR) of the COP control register at location $0FF0
before the COP timer times out. The COP control register is a write-only register
that returns the contents of an EPROM location when read. See
COPR — COP Reset
An opcode fetch from an address that is not in the EPROM (locations
$0700–$0EFF), or the RAM ($0090–$00FF) generates an illegal address reset.
COPR is a write-only bit. Periodically writing a zero to COPR prevents the COP
timer from resetting the MCU.
cyc
cyc
, the MCU remains in the reset condition until the signal on the RESET pin
Bit 7
—
—
(internal clock cycle) delay after the oscillator becomes active allows
Freescale Semiconductor, Inc.
For More Information On This Product,
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—
6
Figure 5-1. COP Control Register
7.3 COP
RESETS AND INTERRUPTS
Go to: www.freescale.com
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5
Timer.) To clear the COP timer and prevent a COP
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cyc
generates an external
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1
Figure
COPR
Bit 0
0
5-1.
$0FF0
Rev. 2