MC33888APNB FREESCALE [Freescale Semiconductor, Inc], MC33888APNB Datasheet - Page 16

• Manufacturer Part Number: MC33888APNB
• Description: Quad High-Side and Octal Low-Side Switch for Automotive
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Table 6. Dynamic Electrical Characteristics (continued)
Typical values noted reflect the approximate parameter means at T
16
33888
ELECTRICAL CONNECTIONS
DYNAMIC ELECTRICAL CHARACTERISTICS
POWER OUTPUT TIMING (continued)
SPI INTERFACE TIMING
Notes
Watchdog Timeout
Peak Current Limit Timer
Direct Input Switching Frequency
Recommended Frequency of SPI Operation
Required Low State Duration for RST
Rising Edge of CS to Falling Edge of CS (Required Setup Time)
Rising Edge of RST to Falling Edge of CS (Required Setup Time)
Falling Edge of CS to Rising Edge of SCLK (Required Setup Time)
Required High State Duration of SCLK (Required Setup Time)
Required Low State Duration of SCLK (Required Setup Time)
Falling Edge of SCLK to Rising Edge of CS (Required Setup Time)
SI to Falling Edge of SCLK (Required Setup Time)
Falling Edge of SCLK to SI (Required Hold Time)
SO Rise Time
SO Fall Time
SI, CS, SCLK, Incoming Signal Rise Time
SI, CS, SCLK, Incoming Signal Fall Time
Time from Falling Edge of CS to SO Low Impedance
Time from Rising Edge of CS to SO High Impedance
Time from Rising Edge of SCLK to SO Data Valid
35.
36.
37.
38.
39.
40.
41.
42.
43.
44.
Characteristics noted under conditions 6.0 V ≤ V
Normal Mode
Extended Mode: V
C
C
0.2 V
L
L
= 200 pF
= 200 pF
Watchdog timeout delay is measured from the rising edge of WAKE or RST from the sleep state to the HS[0:1] turn-ON with the outputs
driven OFF and the FSI floating. The accuracy of t
t
This frequency is a typical value. Maximum switching frequencies are dictated by the turn-ON delay, turn-OFF delay, output rise and fall
times, and the maximum allowable junction temperature.
Symmetrical 50% duty cycle SCLK clock period of 333 ns.
RST low duration measured with outputs enabled and going to OFF or disabled condition.
Maximum setup time required for the 33888 is the minimum guaranteed time needed from the MCU.
Rise and fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
Time required for output status data to be available for use at SO. 1.0 kΩ pullup on CS.
Time required for output status data to be terminated at SO. 1.0 kΩ pullup on CS.
Time required to obtain valid data out from SO following the rise of SCLK.
PCT
DD
measured from the rising edge of CS to 90% of I
≤ SO ≥ 0.8 V
(35)
DD
DD
= 3.4 V; V
(38)
(36)
, C
L
Characteristic
= 200 pF
(37)
PWR
(39)
= 4.5 V, APNB Suffix Only
(41)
(41)
(40)
(44)
(40)
(42)
(43)
PWR
WDTO
LIMPKHS[x,x]
≤ 27 V, 4.5 V ≤ V
(40)
(40)
is maintained for all configured watchdog time-outs.
(40)
(40)
(40)
(40)
when the peak current limit is enabled.
A
= 25°C under nominal conditions unless otherwise noted.
DD
t
Symbol
t
t
t
SI (HOLD)
t
t
WSCLKh
t
t
t
WSCLKl
SO(DIS)
f
t
t
SO(EN)
WDTO
t
SI (SU)
t
≤ 5.5 V, -40°C ≤ T
WRST
t
t
VALID
PWM
f
ENBL
LEAD
t
t
t
PCT
RSO
FSO
LAG
RSI
SPI
FSI
CS
Min
340
40
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Analog Integrated Circuit Device Data
J
≤ 150°C unless otherwise noted.
Typ
584
125
70
50
50
50
25
25
25
25
65
65
–
–
–
–
–
–
–
–
–
Freescale Semiconductor
Max
770
100
167
300
167
167
167
167
145
145
105
3.0
2.1
5.0
83
83
50
50
50
50
–
Unit
MHz
ms
ms
Hz
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns