MC33888APNB FREESCALE [Freescale Semiconductor, Inc], MC33888APNB Datasheet - Page 24

• Manufacturer Part Number: MC33888APNB
• Description: Quad High-Side and Octal Low-Side Switch for Automotive
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

DEVICE REGISTER ADDRESSING
addresses and their impact on device operation.
Address 000 — SPI Output Control Register (SOCR)
via the SPI. Incoming message bits D3 : D0 reflect the desired
states of high-side outputs HS3 : HS0. Message bits D11: D4
reflect the desired state of low-side outputs LS11: LS4,
respectively.
Address 100— Direct Input Control Register (DICR)
input control of the outputs. For the outputs, a logic [0] on bits
D11: D0 will enable the corresponding output for direct
control. A logic [1] on a D11: D0 bit will disable the output from
direct control.
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33888
Table 8. SI Message Bit Assignment (continued)
Table 9. Serial Input Address and Configuration Bit Map
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
WDCSCR
CLOCCR
Register
x = Don’t care.
NA = Not applicable.
SOCR
OLCR
USED
LFCR
DICR
TEST
The following section describes the possible register
The SOCR register allows the MCU to control the outputs
The DICR register is used by the MCU to enable direct
NOT
SI
D15
WD
D9
D8
D7
D6
x
x
x
x
x
x
x
x
D14
0
1
0
1
0
1
0
1
Used to configure Low-Side Output LS9.
Used to configure Low-Side Output LS8.
Used to configure Low-Side Output LS7.
Used to configure Low-Side Output LS6.
Address
D13
0
0
1
1
0
0
1
1
D12
0
0
0
0
1
1
1
1
PWB11 PWB10 PWB9 PWB8 PWB7 PWB6 PWB5 PWB4 PWB3 PWB2 PWB1 PWB0
OB11
OC11
OL11
LS11
D11
NA
A/
–
–
LOGIC COMMANDS AND REGISTERS
OB10
OC10
OL10
LS10
D10
NA
A/
–
–
A/OB9 A/OB8 A/OB7 A/OB6 A/OB5 A/OB4 A/OB3 A/OB2 A/OB1 A/OB0
OC9
LS9
OL9
NA
D9
–
–
OC8
OL8
LS8
NA
D8
Low-Side
–
–
Address 010 — Logic Function Control Register (LFCR)
relationship between SOCR bits D11: D0 and the direct inputs
IHS[0:3] and ILS. While addressing this register (if the direct
inputs were enabled for direct control with the DICR), a
logic [1] on any or all of the D3 : D0 bits will result in a Boolean
AND of the IHS[0:3] pin(s) with its (their) corresponding
D3 : D0 message bit(s) when addressing the SOCR. A
logic [1] on any or all of the D11: D4 bits will result in a
Boolean AND of the ILS and the corresponding D11: D4
message bits when addressing the SOCR. Similarly, a
logic [0] on the D3 : D0 bits will result in a Boolean OR of the
IHS[0:3] pin(s) with their corresponding message bits when
addressing the SOCR register, and the ILS will be Boolean
OR’d with message bits D11: D4 when addressing the SOCR
register (if ILS is enabled).
Table 8. SI Message Bit Assignment (continued)
Bit Sig SI Msg Bit
OC7
OL7
LS7
NA
D7
LSB
–
–
The LFCR register is used by the MCU to configure the
OC6
OL6
LS6
NA
D6
–
–
D5
D4
D3
D2
D1
D0
WDH
OC5
OL5
LS5
D5
–
–
Used to configure Low-Side Output LS5
(Watchdog timeout MSB during WDCSCR
configuration).
Used to configure Low-Side Output LS4
(Watchdog timeout LSB during WDCSCR
configuration).
Used to configure High-Side Output HS3.
Used to configure High-Side Output HS2.
Used to configure High-Side Output HS1.
Used to configure High-Side Output HS0.
Analog Integrated Circuit Device Data
WDL
OC4
OL4
LS4
D4
–
–
Message Bit Description
ILIMPK
OLB3
ILIM3
HS3
CS3
D3
–
Freescale Semiconductor
OLB2
ILIM2
HS2
CS2
WD
D2
High-Side
–
OLB1
ILIM1
HS1
CS1
ILIM
D1
–
OLB0
ILIM0
HS0
CS0
OT
D0
–