FDC37B80X SMSC [SMSC Corporation], FDC37B80X Datasheet - Page 101

• Manufacturer Part Number: FDC37B80X
• Description: PC98/99 Compliant Enhanced Super I/O Controller with Keyboard/Mouse Wake-Up
• Manufacturer: SMSC [SMSC Corporation]

An interrupt is generated when serviceIntr is 0
and the number of bytes in the FIFO is greater
than or equal to (16-<threshold>). (If the
threshold = 12, then the interrupt is set
whenever there are 4-16 bytes in the FIFO). The
PINT pin can be used for interrupt-driven
systems. The host must respond to the request
by reading data from the FIFO. This process is
repeated until the last byte is transferred out of
the FIFO. If at this time the FIFO is full, it can
be completely emptied in a single burst,
otherwise a minimum of (16-<threshold>) bytes
may be read from the FIFO in a single burst.
Programmed I/O - Transfers from the Host to
the FIFO
In the forward direction an interrupt occurs when
serviceIntr is 0 and there are writeIntrThreshold
or more bytes free in the FIFO. At this time if
the FIFO is empty it can be filled with a single
101
burst before the empty bit needs to be re-read.
Otherwise
writeIntrThreshold bytes.
writeIntrThreshold =
An interrupt is generated when serviceIntr is 0
and the number of bytes in the FIFO is less than
or equal to <threshold>. (If the threshold = 12,
then the interrupt is set whenever there are 12 or
less bytes of data in the FIFO.) The PINT pin
can be used for interrupt-driven systems. The
host must respond to the request by writing data
to the FIFO. If at this time the FIFO is empty, it
can be completely filled in a single burst,
otherwise a minimum of (16-<threshold>) bytes
may be written to the FIFO in a single burst.
This process is repeated until the last byte is
transferred into the FIFO.
it
may
(16-<threshold>) free
bytes in FIFO
be
filled
with