FDC37B80X SMSC [SMSC Corporation], FDC37B80X Datasheet - Page 170

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FDC37B80X

Manufacturer Part Number
FDC37B80X
Description
PC98/99 Compliant Enhanced Super I/O Controller with Keyboard/Mouse Wake-Up
Manufacturer
SMSC [SMSC Corporation]
Datasheet
Note:
Note:
CLOCKI
RESET_DRV
NAME
NAME
t1
t2
t4
Tolerance is
The RESET width is dependent upon the processor clock. The RESET must be active while
the clock is running and stable.
Clock Cycle Time for 14.318MHz (Note)
Clock High Time/Low Time for 14.318MHz
Clock Rise Time/Fall Time (not shown)
RESET width (Note)
0.01%
DESCRIPTION
DESCRIPTION
FIGURE 7A - INPUT CLOCK TIMING
FIGURE 7B - RESET TIMING
t1
170
t4
t2
MIN
20
MIN
1.5
69.84
TYP
t2
TYP
35
MAX
MAX
5
UNITS
UNITS
ns
ns
ns
s

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