FDC37B80X SMSC [SMSC Corporation], FDC37B80X Datasheet - Page 110

• Manufacturer Part Number: FDC37B80X
• Description: PC98/99 Compliant Enhanced Super I/O Controller with Keyboard/Mouse Wake-Up
• Manufacturer: SMSC [SMSC Corporation]

The SMI is enabled onto the SMI frame of the
Serial IRQ via bit 6 of SMI Enable Register 2.
SERIAL INTERRUPTS
The FDC37B80x will support the serial interrupt
to transmit interrupt information to the host
PCICLK
IRQSER
Drive Source
A) Start Frame timing with source sampled a low pulse on IRQ1
1) Start Frame pulse can be 4-8 clocks wide.
IRQ1
SL
or
H
H=Host Control
SL=Slave Control
START
Host Controller
START FRAME
H
1
S=Sample
SERIAL IRQ
R
110
T
R=Recovery
T=Turn-around
system. The serial interrupt scheme adheres to
the Serial IRQ Specification for PCI Systems,
Version 6.0.
Timing Diagrams For IRQSER Cycle
IRQ0 FRAME IRQ1 FRAME
S
None
R
PCICLK = 33MHz_IN pin
IRQSER = SIRQ pin
T
S
IRQ1
R
T
IRQ2 FRAME
S
None
R
T