ISL6112 INTERSIL [Intersil Corporation], ISL6112 Datasheet - Page 11

• Manufacturer Part Number: ISL6112
• Description: Dual Slot PCI-Express Power Controller
• Manufacturer: INTERSIL [Intersil Corporation]

ISL6112 Bias, Power-On Reset and Power Cycling
The ISL6112 utilizes VSTBY as the only supply source.
VSTBY is required for proper operation of the ISL6112’s
SMBus and registers and must be applied at all times. A
Power-On Reset (POR) cycle is initiated after VSTBY rises
above its UVLO threshold and remains satisfied for 250µs.
All internal registers are cleared after POR. If VSTBY is
recycled, the ISL6112 enters a new power-on-reset cycle.
VSTBY must be the first supply voltage applied followed by
the MAIN supply inputs of 12VIN and 3VIN. The SMBus is
ready for access at the end of the POR cycle (250µs after
VSTBY is valid). During t
Enabling the VAUX Outputs
Upon asserting an AUXEN input, the related internal power
switch turns on connecting the nominally 3.3V VSTBY
supply to its VAUX load. The turn-on is slew rate limited and
invokes the ICs current regulation feature so as to not droop
the supply due to in-rush current load. Figure 2 illustrates the
VAUX turn-on performance into a 10Ω, 100µF load.
Standby Mode
Standby mode is entered when one or more of the MAIN
supply inputs (12VIN and/or 3VIN) is absent, below its
respective UVLO threshold or OFF. The ISL6112 also has
3.3V auxiliary outputs (VAUXA and VAUXB), satisfying an
optional PCI Express requirement. These outputs are fed
from the VSTBY input pins, they are independent of the
MAIN outputs and are controlled by the AUXEN input pins or
via their respective bits in the control registers. Should the
MAIN supply inputs fall below their respective UVLO
thresholds, VAUX will still function as long as VSTBY is
compliant. Prior to standby mode, ONA and ONB (or the
control registers' MAINA and MAINB bits) inputs must be
FIGURE 1. I/O CONFIGURATION FOR DISABLING HPI/SMI
DISABLING SMI WHEN HPI CONTROL IS USED
DISABLING HPI WHEN SMI CONTROL IS USED
V
INT
STBY
V
CONTROL
STBY
POR
100k
100k
100k
100k
100k
11
, all outputs remain off.
28
45
42
44
43
9
FORON#_A
FORON#_B
AUXENA
AUXENB
ONA
ONB
SCL
SDA
INT#
A2
A1
A0
ISL6112
deasserted or else the ISL6112 will assert its FAULT outputs.
If an undervoltage condition on either of the MAIN supply
inputs is detected, the INT will also assert if interrupts are
enabled.
Enabling the MAIN GATE outputs
When a slot's MAIN supplies are off, the 12VGATE pin is
held high with an internal pull-up to the 12VIN voltage.
Similarly, the 3VGATE pin is internally held low to GND.
When the MAIN supplies of the ISL6112 are enabled by
asserting ON, the related 3VGATE and 12VGATE pins are
each connected to a constant current supply. For the
3VGATE pin, this is nominally a 25µA current source and for
the 12VGATE pin, this is nominally a -25µA current sink. The
3VGATE will be charged up to the 12VIN voltage whereas
the 12GATE will be pulled down to GND for maximum
enhancement of the N-Channel and P-Channel FETs,
respectively.
Estimating In-Rush Current and V
Start-up
The expected in-rush current can be estimated by using
Equation 1:
with 25µA being the GATE pin charge current, C
load capacitance, and C
including C
capacitance connected from the GATE output pin to the
GATE reference, GND or source.
An estimate for the output slew rate of 3.3V outputs and 12V
outputs where there is little or no external 12VGATE output
capacitors, can be had from Equation 2:
I
dv/dt VOUT NOMINALLY
IN RUSH
FIGURE 2. VAUX TURN-ON R
–
NOMINALLY
ISS
of the external MOSFET and any external
=
GATE
=
25μA
------------------- -
C
I
LOAD
LIM
is the total GATE capacitance
LOAD
⎛
⎜
⎝
C
------------------- -
C
LOAD
GATE
= 10Ω, C
⎞
⎟
⎠
OUT
IAUX
IAUX
VAUX
VAUX
AUXEN
AUXEN
LOAD
Slew Rate at
September 28, 2007
LOAD
= 100µF
(EQ. 1)
FN6456.0
(EQ. 2)
is the