ISL6112 INTERSIL [Intersil Corporation], ISL6112 Datasheet - Page 12

• Manufacturer Part Number: ISL6112
• Description: Dual Slot PCI-Express Power Controller
• Manufacturer: INTERSIL [Intersil Corporation]

where I
capacitance. As a consequence, the CR duration, t
must be programmed to exceed the time it will take to fully
charge the output load to the input rail voltage level.
MAIN Outputs (Start-up Delay and Slew-Rate
Control)
The 3.3V outputs act as source followers. In this mode of
operation, V
associated output reaches 3.3V. The voltage on the gate of
the MOSFET will then continue to rise until it reaches 12V,
which ensures minimum r
the MOSFET is optionally configured as a Miller integrator to
adjust the V
which is connected between the MOSFET’s gate and drain.
In this configuration, the feedback action from drain to gate
of the MOSFET causes the voltage at the drain of the
MOSFET to slew in a linear fashion at a rate estimated by
Equation 3:
Table 1 approximates the output slew-rate for various values
of C
(external C
external MOSFET for the 3.3V rail; C
Note that all of these performance estimates are useful only for
first order time and loading expectations as they do not look at
other significant loading factors. Figures 3, 4, 5, 6 and 7
illustrate empirically the discussed turn-on performance with the
noted loading and compensation conditions.
Notice the degree of control over the in-rush current and the
GATE ramp rate as the and values are changed thus providing
for highly customizable turn-on characteristics.
In some scope shots although the C
in the absence of excessive displayed loading current the
C
is not displayed.
All scope shots were taken from the ISL6112EVAL1Z with
any component changes noted.
dv/dt VOUT NOMINALLY
CGATE or C
0.01µF*
0.022µF*
0.047µF
0.1µF
*
capacitances of the MOSFETs used, and should be verified
experimentally.
Values in this range will be affected by the internal parasitic
FILTER
TABLE 1. 3.3V AND 12V OUTPUT SLEW-RATE SELECTION
GATE
LIM
is responding to the other MAIN supply current that
when start-up is dominated by GATE capacitance
GATE
= 50mV/R
GD
OUT
SOURCE
FOR GATE CAPACITANCE DOMINATED START-UP
ramp time by having a C
from GATE pin to ground plus C
SENSE
= [V
| IGATE | = 25µA
=
DS(ON)
GATE
25μA
-------------- -
C
GD
12
and C
– V
. For the 12V outputs, when
dv/dt (load)
2.5V/ms
1.136V/ms
0.532 V/ms
0.250V/ms
TH(ON)
LOAD
FILTER
GD
for the 12V rail).
is the load
GD
] until the
shows a ramping
capacitor,
GS
FILTER,
of the
(EQ. 3)
ISL6112
FIGURE 4. 3VMAIN START-UP R
FIGURE 3. 12VMAIN START-UP R
FIGURE 5. 12VMAIN START-UP RLOAD = 10Ω,
C
FILTER
RESPONDING TO UNSHOWN MAIN SUPPLY
C
C
LOAD
LOAD
= 470µF
= 470µF
LOAD
LOAD
= 2Ω, C
= 10Ω,
C
C
C
C
C
GD
GS
GD
GS
GATE
LOAD
= 6800pF
= 2200pF
= 6800pF
= 22nF
September 28, 2007
= 22nF
C
12I
C
C
3I
12I
12V
12V
3V
12V
FILTER
FILTER
FILTER
3V
12V
OUT
= 470µF
OUT
GATE
OUT
GATE
OUT
OUT
GATE
FN6456.0
OUT