ISL6267 INTERSIL [Intersil Corporation], ISL6267 Datasheet - Page 15

• Manufacturer Part Number: ISL6267
• Description: Multiphase PWM Regulator for AMD Fusion Mobile CPUs
• Manufacturer: INTERSIL [Intersil Corporation]

Diode Emulation and Period Stretching
The ISL6267 can operate in diode emulation (DE) mode to
improve light-load efficiency. In DE mode, the low-side MOSFET
conducts when the current is flowing from source to drain and
does not allow reverse current, thus emulating a diode. As Figure
10 shows, when LGATE is on, the low-side MOSFET carries current,
creating negative voltage on the phase node due to the voltage
drop across the ON-resistance. The ISL6267 monitors the current
by monitoring the phase node voltage. It turns off LGATE when the
phase node voltage reaches zero to prevent the inductor current
from reversing the direction and creating unnecessary power loss.
If the load current is light enough, as Figure 10 shows, the
inductor current reaches and stays at zero before the next phase
node pulse, and the regulator is in discontinuous conduction
mode (DCM). If the load current is heavy enough, the inductor
current will never reaches 0A, and the regulator is in CCM,
although the controller is in DE mode.
Figure 11 shows the operation principle in diode emulation mode
at light load. The load gets incrementally lighter in the three cases
from top to bottom. The PWM on-time is determined by the VW
window size and therefore is the same, making the inductor
current triangle the same in the three cases. The ISL6267 clamps
the ripple capacitor voltage V
inductor current. It takes the COMP voltage longer to hit V
naturally stretching the switching period. The inductor current
triangles move farther apart such that the inductor current
average value is equal to the load current. The reduced switching
frequency helps increase light-load efficiency.
MASTER
CLOCK1
CLOCK2
CLOCK3
CLOCK
FIGURE 9. R
PWM1
PWM2
PWM3
V
CRM
INSERTION RESPONSE
3
™
MODULATOR OPERATION PRINCIPLES IN LOAD
VCRS2
VCRS1
COMP
VCRS3
VW
CRS
15
VW
in DE mode to make it mimic the
CRS
ISL6267
,
Start-up Timing
With the controller's V
threshold, the start-up sequence begins when ENABLE exceeds the
logic high threshold. Figure 12 shows the typical start-up timing of
VR1 and VR2. The ISL6267 uses digital soft-start to ramp-up DAC
to the voltage programmed by the Metal VID. PGOOD is asserted
high and low at the end of the ramp up. Similar results occur if
ENABLE is tied to V
800µs after V
P H A S E
U G A T E
L G A T E
V
V
V
IL
CRS
CRS
CRS
IL
IL
IL
DD
FIGURE 10. DIODE EMULATION
FIGURE 11. PERIOD STRETCHING
crosses the POR threshold.
DD
DD
, with the soft-start sequence starting
VW
VW
VW
and V
BOUNDARY
LIGHT DCM
DEEP DCM
CCM/DCM
IN
voltages above their POR
January 31, 2011
FN7801.0