ISL6267 INTERSIL [Intersil Corporation], ISL6267 Datasheet - Page 20

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ISL6267

Manufacturer Part Number
ISL6267
Description
Multiphase PWM Regulator for AMD Fusion Mobile CPUs
Manufacturer
INTERSIL [Intersil Corporation]
Datasheet

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Part Number:
ISL6267HRZ
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Quantity:
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As the load current increases from zero, the output voltage
droops from the VID table value by an amount proportional to the
load current, to achieve the load line. The ISL6267 can sense the
inductor current through the intrinsic DC Resistance (DCR) of the
inductors, as shown in Figures 15 and 16, or through resistors in
series with the inductors as shown in Figure 17. In both methods,
capacitor C
droop amplifier converts C
source with the gain set by resistor R
for load line implementation, current monitoring and overcurrent
protection.
Figure 15 shows the load-line implementation. The ISL6267
drives a current source (I
Equation 1.
When using inductor DCR current sensing, a single NTC element
is used to compensate the positive temperature coefficient of the
copper winding, thus sustaining the load-line accuracy with
reduced cost.
I
shown in Equation 2.
V
Changing R
Since I
recommended to first scale I
then select an appropriate R
load line slope.
Differential Sensing
Figure 15 also shows the differential voltage sensing scheme.
VCC
from the processor die. A unity gain differential amplifier senses
the VSS
I
V
droop
droop
droop
droop
FIGURE 15. DIFFERENTIAL SENSING AND LOAD LINE
SENSE
COMP
flows through resistor R
droop
=
is the droop voltage required to implement load line.
=
SENSE
2xV
----------------
R
and VSS
INTERNAL TO IC
n
R
droop
droop
also sets the overcurrent protection level, it is
i
voltage represents the inductor total currents. A
Cn
IMPLEMENTATION
voltage and adds it to the DAC output. The error
E/A
×
or scaling I
+
-
I
SENSE
droop
FB
Σ
droop
+
are the remote voltage sensing signals
Idroop
VDAC
n
droop
voltage into an internal current
droop
droop
+
Rdroop
20
Vdroop
droop
) out of the FB pin, as described by
DAC
X 1
can change the load line slope.
value to obtain the desired
-
based on OCP requirement,
+
-
and creates a voltage drop as
i
. The current source is used
RTN
VSS
VIDs
“CATCH” RESISTOR
“CATCH” RESISTOR
VCC
VSS
VID<0:7>
SENSE
VR LOCAL VO
SENSE
(EQ. 1)
(EQ. 2)
ISL6267
amplifier regulates the inverting and non-inverting input voltages
to be equal as shown in Equation 3:
Rewriting Equation 3 and substituting Equation 2 gives
Equation 4 is the exact equation required for load-line
implementation.
The VCC
The feedback is, open circuit in the absence of the processor. As
Figure 15 shows, it is recommended to add a “catch” resistor to feed
the VR local output voltage back to the compensator, and to add
another “catch” resistor to connect the VR local output ground to the
RTN pin. These resistors, typically 10Ω~100Ω, provide voltage
feedback if the system is powered up without a processor installed.
Phase Current Balancing
The ISL6267 monitors individual phase average current by
monitoring the ISEN1, ISEN2, and ISEN3 voltages. Figure 16
shows the current balancing circuit recommended for ISL6267.
Each phase node voltage is averaged by a low-pass filter
consisting of R
corresponding ISEN pin. R
phase-node pad in order to eliminate the effect of phase node
parasitic PCB DCR. Equations 5 through 7 give the ISEN pin
voltages:
where R
and R
side pad and the output voltage rail; and I
inductor average currents.
VCC
V
VCC
V
V
ISEN1
ISEN2
ISEN3
INTERNAL
INTERNAL
SENSE
SENSE
TO IC
pcb3
=
SENSE
=
=
ISEN3
ISEN2
ISEN1
dcr1
(
(
(
+
R
R
R
are parasitic PCB DCR between the inductor output
FIGURE 16. CURRENT BALANCING CIRCUIT
VSS
V
dcr2
dcr1
dcr3
, R
droop
and VSS
isen
dcr2
PHASE3
SENSE
+
+
+
PHASE2
PHASE1
R
R
R
and C
=
and R
pcb1
pcb2
pcb3
C
C
C
V
R
R
R
SENSE
isen
isen
isen
=
DAC
isen
isen
isen
)
)
)
isen
V
×
×
dcr3
×
isen
DAC
+
I
I
I
L2
L1
L3
signals come from the processor die.
, and is presented to the
VSS
are inductor DCR; R
should be routed to the inductor
R
SENSE
droop
L3
L2
L1
I
I
I
L3
L2
L1
×
I
droop
R
R
R
L1
dcr3
dcr2
dcr1
, I
L2
R
R
R
pcb3
pcb2
pcb1
and I
pcb1
January 31, 2011
L3
, R
are
V
pcb2
FN7801.0
(EQ. 5)
(EQ. 6)
(EQ. 7)
(EQ. 3)
(EQ. 4)
O

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