ISL6322 INTERSIL [Intersil Corporation], ISL6322 Datasheet - Page 29

• Manufacturer Part Number: ISL6322
• Description: Four-Phase Buck PWM Controller with Integrated MOSFET Drivers and I2C Interface for Intel VR10, VR11, and AMD Applications
• Manufacturer: INTERSIL [Intersil Corporation]

RGS1 and receiving an Acknowledge from the ISL6322,
instead of sending a Stop condition, the master sends the
data byte to be stored in register RGS2. The ISL6322 will
respond with an Acknowledge. The master then issues a
I
Reading from the Internal Registers
The ISL6322 has the ability to read from both registers
separately or read from them consecutively. Prior to reading
from an internal register, the master must first select the
desired register by writing to it and sending the register’s
address byte. This process begins by the master sending a
control byte with the R/W bit set to 0, indicating a write. Once
it receives an Acknowledge from the ISL6322, it sends a
register address byte representing the internal register it
wants to read from (0000_0000 for RGS1 or 0000_0001 for
RGS2). The ISL6322 will respond with an Acknowledge. The
master must then respond with a Stop condition. After the
Stop condition, the master follows with a new Start condition,
and then sends a new control byte with the R/W bit set to 1,
indicating a read. The ISL6322 will then respond by sending
the master an Acknowledge, followed by the data byte
stored in that register. The master must then send a Not
Acknowledge followed by a Stop command, which will
complete the read transaction.
It is also possible for both registers to be read consecutively.
To do this the master must read from register RGS1 first.
This transaction begins with the master sending a control
byte with the R/W bit set to 0. If it receives an Acknowledge
from the ISL6322, it sends the register address byte
0000_0000, representing the internal register RGS1. The
ISL6322 will respond with an Acknowledge. The master
must then respond with a Stop condition. After the Stop
condition the master follows with a new Start condition, and
then sends a new control byte with the R/W bit set to 1,
indicating a read. The ISL6322 will then respond by sending
2
Write to a Single Register
Write to Both Registers
Read from a Single Register
Read from Both Registers
S
S
S
S
C Read and Write Protocol
Driven by Master
Driven by ISL6322
slave_addr + W
slave_addr + W
slave_addr + W
slave_addr + W
A
A
A
A
29
0000_0000
0000_0000
reg_addr
reg_addr
S = START Condition
P = STOP Condition
A
A
A
A
P
P
reg_RGS1_data
reg_data
S
S
A = Acknowledge
N = No Acknowledge
ISL6322
slave_addr + R
slave_addr + R
A
A
Stop condition, indicating to the ISL6322 that the current
transaction is complete. Once this transaction completes the
ISL6322 will immediately update and change the operating
parameters on-the-fly.
the master an Acknowledge, followed by the data byte
stored in register RGS. The master must then send an
Acknowledge, and after doing so, the ISL6322 will respond
by sending the data byte stored in register RGS2. The
master must then send a Not Acknowledge followed by a
Stop command, which will complete the read transaction.
Resetting the Internal Registers
The ISL6322’s two internal I
0000_0000 when the controller first receives power. Once
the voltage on the VCC pin rises above the POR rising
threshold level, these registers can be changed at any time
via the I
below the POR falling threshold, the internal registers are
automatically reset to 0000_0000.
It is possible to reset the internal registers without powering
down the controller and without requiring the controller to
stop regulating and soft-start again. This can be done by one
of two methods. The first method is to simply write to the
internal registers over the I
The other method is pull the voltage on the SS/RST/A0 pin
down below 0.4V. This will immediately reset the internal
registers to 0000_0000 and will not stop the controller from
regulating the output voltage or cause soft-start to recycle.
P
reg_RGS2_data
A
A
2
C interface. If the voltage on the VCC pin falls
reg_RGS1_data
reg_data
A
P
2
C interface to be 0000_0000.
2
C registers always initialize to
N
A
P
reg_RGS2_data
August 21, 2006
N
FN6328.0
P