ISL6322 INTERSIL [Intersil Corporation], ISL6322 Datasheet - Page 35

• Manufacturer Part Number: ISL6322
• Description: Four-Phase Buck PWM Controller with Integrated MOSFET Drivers and I2C Interface for Intel VR10, VR11, and AMD Applications
• Manufacturer: INTERSIL [Intersil Corporation]

Compensation
The two opposing goals of compensating the voltage
regulator are stability and speed. Depending on whether the
regulator employs the optional load-line regulation as
described in “Load-Line (Droop) Regulation” on page 20,
there are two distinct methods for achieving these goals:
“Compensation with Load-line Regulation” on page 35 and
“Compensation without Load-line Regulation” on page 35.
Compensation with Load-line Regulation
The load-line regulated converter behaves in a similar
manner to a peak current mode controller because the two
poles at the output filter L-C resonant frequency split with the
introduction of current information into the control loop. The
final location of these poles is determined by the system
function, the gain of the current signal, and the value of the
compensation components, R
Since the system poles and zero are affected by the values
of the components that are meant to compensate them, the
solution to the system equation becomes fairly complicated.
Fortunately, there is a simple approximation that comes very
close to an optimal solution. Treating the system as though it
were a voltage-mode regulator, by compensating the L-C
poles and the ESR zero of the voltage mode approximation,
yields a solution that is always stable with very close to ideal
transient performance.
Select a target bandwidth for the compensated system, f
The target bandwidth must be large enough to assure
adequate transient performance, but smaller than 1/3 of the
per-channel switching frequency. The values of the
compensation components depend on the relationships of f
to the L-C pole frequency and the ESR zero frequency. For
each of the following three, there is a separate set of
equations for the compensation components.
FIGURE 23. COMPENSATION CONFIGURATION FOR
R
FB
LOAD-LINE REGULATED ISL6322 CIRCUIT
R
C
C
2
C
(OPTIONAL)
C
35
C
and C
IDROOP
COMP
VDIFF
FB
C
.
ISL6322
0
.
0
ISL6322
In Equation 41:
- L is the per-channel filter inductance divided by the
- C is the sum total of all output capacitors,
- ESR is the equivalent series resistance of the bulk output
- V
Once selected, the compensation values in Equation 41
assure a stable converter with reasonable transient
performance. In most cases, transient performance can be
improved by making adjustments to R
value of R
oscilloscope until no further improvement is noted. Normally,
C
case equations in Equation 41 unless some performance
issue is noted.
Case 3:
The optional capacitor C
noise away from the PWM comparator (see Figure 23). Keep
a position available for C
high-frequency capacitor of between 22pF and 150pF in
case any leading edge jitter problem is noted.
Compensation without Load-line Regulation
The non load-line regulated converter is accurately modeled
as a voltage-mode regulator with two poles at the L-C
resonant frequency and a zero at the ESR frequency. A
Case 2:
Case 1:
C
number of active channels,
filter capacitance, and
described in the Electrical Specifications on page 7.
PP
will not need adjustment. Keep the value of C
is the peak-to-peak sawtooth signal amplitude as
C
while observing the transient performance on an
------------------------------- -
2 π
R
C
C
C
⋅
------------------------------- -
2 π
R
C
f
R
C
C
C
⋅
=
=
0
⋅
1
C
C
>
R
=
=
-------------------------------------------------------------------------------------
(
⋅
L C
2 π
1
------------------------------------ -
2 π C ESR
=
=
FB
R
--------------------------------------------------- -
2 π V
⋅
⋅
L C
⋅
R
----------------------------------------------------------------
2 π V
FB
⋅
⋅
⋅
)
0.66 V
FB
⋅
≤
V
---------------------------------------------------------------- -
2
⋅
2
2
⋅
⋅
0.66 V
PP
f
⋅
, is sometimes needed to bypass
1
, and be prepared to install a
>
0
2 π f
------------------------------------------------------- -
⋅
⋅
f
⋅
PP
<
0
f
⋅
-------------------------------------------- -
0.66 V
⋅
2 π f
0
⋅
2
0.66 V
PP
------------------------------------ -
2 π C ESR
(
⋅
⋅
⋅
2 π ⋅
0.66 V
IN
⋅
⋅
⋅
V
0.66 V
R
⋅
0
IN
PP
⋅
⋅
⋅
R
FB
⋅
⋅
⋅
ESR
)
0
FB
V
⋅
2
1
IN
IN
⋅
⋅
⋅
⋅
pp
⋅
R
⋅
V
f
⋅
0
C
IN
⋅
f
FB
IN
pp
f
0
⋅
ESR
⋅
0
. Slowly increase the
2
⋅
⋅
⋅
⋅
L C
C
L C
L
⋅
L
⋅
L C
⋅
August 21, 2006
C
from the
(EQ. 41)
FN6328.0