ISL6322 INTERSIL [Intersil Corporation], ISL6322 Datasheet - Page 37

• Manufacturer Part Number: ISL6322
• Description: Four-Phase Buck PWM Controller with Integrated MOSFET Drivers and I2C Interface for Intel VR10, VR11, and AMD Applications
• Manufacturer: INTERSIL [Intersil Corporation]

The filter capacitor must have sufficiently low ESL and ESR
so that ΔV < ΔV
Most capacitor solutions rely on a mixture of high-frequency
capacitors with relatively low capacitance in combination
with bulk capacitors having high capacitance but limited
high-frequency performance. Minimizing the ESL of the
high-frequency capacitors allows them to support the output
voltage as the current increases. Minimizing the ESR of the
bulk capacitors allows them to supply the increased current
with less output voltage deviation.
The ESR of the bulk capacitors also creates the majority of
the output-voltage ripple. As the bulk capacitors sink and
source the inductor ac ripple current (see “Interleaving” on
page 11 and Equation 2), a voltage develops across the bulk
capacitor ESR equal to I
capacitors are selected, the maximum allowable ripple
voltage, V
inductance.
Since the capacitors are supplying a decreasing portion of
the load current while the regulator recovers from the
transient, the capacitor voltage becomes slightly depleted.
The output inductors must be capable of assuming the entire
load current before the output voltage decreases more than
ΔV
Equation 45 gives the upper limit on L for the cases when
the trailing edge of the current transient causes a greater
output-voltage deviation than the leading edge. Equation 46
addresses the leading edge. Normally, the trailing edge
dictates the selection of L because duty cycles are usually
less than 50%. Nevertheless, both inequalities should be
evaluated, and L should be selected based on the lower of
the two results. In each equation:
L is the per-channel inductance,
C is the total output capacitance, and
N is the number of active channels.
Switching Frequency
There are a number of variables to consider when choosing
the switching frequency, as there are considerable effects on
the upper MOSFET loss calculation. These effects are
outlined in MOSFETs, and they establish the upper limit for
the switching frequency. The lower limit is established by the
L
L
L
≤
≤
≥
MAX
2 N C V
---------------------------------
1.25 N C
---------------------------- -
ESR
⋅
(
(
ΔI
. This places an upper limit on inductance.
ΔI
⋅
⋅
⋅
)
)
2
PP(MAX)
⎛
⎝
------------------------------------------------------------------- -
2
⋅
V
⋅
IN
f
O
S
⋅
–
⋅
⋅
MAX
ΔV
V
N V
ΔV
IN
, determines the lower limit on the
⋅
MAX
.
⋅
MAX
OUT
V
PP MAX
–
C,PP
–
(
(
⎞ V
⎠
ΔI ESR
(
⋅
ΔI ESR
⋅
37
OUT
(ESR). Thus, once the output
⋅
)
)
)
⋅
⎛
⎝
V
IN
–
V
O
⎞
⎠
(EQ. 45)
(EQ. 46)
(EQ. 44)
ISL6322
requirement for fast transient response and small output-
voltage ripple as outlined in “Compensation without Load-
line Regulation” on page 35. Choose the lowest switching
frequency that allows the regulator to meet the transient-
response requirements.
Switching frequency is determined by the selection of the
frequency-setting resistor, R
are provided to assist in selecting the correct value for R
R T
Input Capacitor Selection
The input capacitors are responsible for sourcing the ac
component of the input current flowing into the upper
MOSFETs. Their RMS current capacity must be sufficient to
handle the ac component of the current drawn by the upper
MOSFETs which is related to duty cycle and the number of
active phases.
FIGURE 26. NORMALIZED INPUT-CAPACITOR RMS CURRENT
0.3
0.2
0.1
=
1000
0
10
100
0
10
I
I
L,PP
L,PP
[
10.61
FIGURE 25. R
10
= 0
= 0.25 I
vs DUTY CYCLE FOR 4-PHASE CONVERTER
–
0.2
(
1.035
O
SWITCHING FREQUENCY (kHz)
⋅
T
DUTY CYCLE (V
100
log
vs SWITCHING FREQUENCY
0.4
(
f S
T
. Figure 25 and Equation 47
)
I
I
)
L,PP
L,PP
]
= 0.5 I
= 0.75 I
0.6
O/
1000
V
O
IN
O
)
0.8
August 21, 2006
10000
(EQ. 47)
FN6328.0
T
1.0
.