SAF-XC164CS-8F20F INFINEON [Infineon Technologies AG], SAF-XC164CS-8F20F Datasheet - Page 22

• Manufacturer Part Number: SAF-XC164CS-8F20F
• Description: 16-Bit Single-Chip Microcontroller
• Manufacturer: INFINEON [Infineon Technologies AG]

3.3
The main core of the CPU consists of a 5-stage execution pipeline with a 2-stage
instruction-fetch pipeline, a 16-bit arithmetic and logic unit (ALU), a 32-bit/40-bit multiply
and accumulate unit (MAC), a register-file providing three register banks, and dedicated
SFRs. The ALU features a multiply and divide unit, a bit-mask generator, and a barrel
shifter.
Figure 4
Based on these hardware provisions, most of the XC164’s instructions can be executed
in just one machine cycle which requires 25 ns at 40 MHz CPU clock. For example, shift
and rotate instructions are always processed during one machine cycle independent of
the number of bits to be shifted. Also multiplication and most MAC instructions execute
in one single cycle. All multiple-cycle instructions have been optimized so that they can
be executed very fast as well: for example, a 32-/16-bit division is started within 4 cycles,
while the remaining 15 cycles are executed in the background. Another pipeline
Data Sheet
Internal Program Memory
SRAM
MAC
CPU
Prefetch Unit
Branch Unit
Multiply Unit
IDX0
IDX1
MAH
FIFO
QX0
QX1
+/-
+/-
Central Processing Unit (CPU)
CPU Block Diagram
Return Stack
CPUCON1
CPUCON2
MRW
MCW
MSW
CSP
MAL
CPUID
QR0
QR1
+/-
IP
PMU
DMU
IFU
Division Unit
Multiply Unit
DPP0
DPP1
DPP2
DPP3
Zeros
MDC
PSW
MDH
Peripheral-Bus
Injection/Exception
Bit-Mask-Gen.
Handler
Barrel-Shifter
VECSEG
SPSEG
STKOV
STKUN
Ones
MDL
TFR
SP
+/-
18
ADU
ALU
System-Bus
RF
System-Bus
Buffer
GPRs
2-Stage
5-Stage
R15
R14
CP
R1
R0
Prefetch
Pipeline
GPRs
Pipeline
R15
R14
R1
R0
GPRs
R15
R14
R1
R0
WB
IPIP
Functional Description
Derivatives
address
V2.1, 2003-06
data in
data out
DPRAM
GPRs
R15
R14
R1
R0
XC164