SAF-XC164CS-8F20F INFINEON [Infineon Technologies AG], SAF-XC164CS-8F20F Datasheet - Page 42

• Manufacturer Part Number: SAF-XC164CS-8F20F
• Description: 16-Bit Single-Chip Microcontroller
• Manufacturer: INFINEON [Infineon Technologies AG]

Summary of Features
• CAN functionality according to CAN specification V2.0B active.
• Data transfer rate up to 1 Mbit/s
• Flexible and powerful message transfer control and error handling capabilities
• Full-CAN functionality and Basic CAN functionality for each message object
• 32 flexible message objects
• Up to eight individually programmable interrupt nodes can be used
• CAN Analyzer Mode for bus monitoring is implemented
Note: When a CAN node has the interface lines assigned to Port 4, the segment address
3.14
The Watchdog Timer represents one of the fail-safe mechanisms which have been
implemented to prevent the controller from malfunctioning for longer periods of time.
The Watchdog Timer is always enabled after a reset of the chip, and can be disabled
until the EINIT instruction has been executed (compatible mode), or it can be disabled
and enabled at any time by executing instructions DISWDT and ENWDT (enhanced
mode). Thus, the chip’s start-up procedure is always monitored. The software has to be
designed to restart the Watchdog Timer before it overflows. If, due to hardware or
software related failures, the software fails to do so, the Watchdog Timer overflows and
generates an internal hardware reset and pulls the RSTOUT pin low in order to allow
external hardware components to be reset.
The Watchdog Timer is a 16-bit timer, clocked with the system clock divided by 2/4/128/
256. The high byte of the Watchdog Timer register can be set to a prespecified reload
value (stored in WDTREL) in order to allow further variation of the monitored time
interval. Each time it is serviced by the application software, the high byte of the
Watchdog Timer is reloaded and the low byte is cleared. Thus, time intervals between
13 s and 419 ms can be monitored (@ 40 MHz).
The default Watchdog Timer interval after reset is 3.28 ms (@ 40 MHz).
Data Sheet
– Assignment to one of the two CAN nodes
– Configuration as transmit object or receive object
– Concatenation to a 2-, 4-, 8-, 16-, or 32-message buffer with FIFO algorithm
– Handling of frames with 11-bit or 29-bit identifiers
– Individual programmable acceptance mask register for filtering for each object
– Monitoring via a frame counter
– Configuration for Remote Monitoring Mode
output on Port 4 must be limited. CS lines can be used to increase the total amount
of addressable external memory.
Watchdog Timer
38
Functional Description
Derivatives
V2.1, 2003-06
XC164