SAF-XC164CS-8F20F INFINEON [Infineon Technologies AG], SAF-XC164CS-8F20F Datasheet - Page 60
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SAF-XC164CS-8F20F
Manufacturer Part Number
SAF-XC164CS-8F20F
Description
16-Bit Single-Chip Microcontroller
Manufacturer
INFINEON [Infineon Technologies AG]
Datasheet
1.SAF-XC164CS-8F20F.pdf
(71 pages)
- Current page: 60 of 71
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5
5.1
The internal operation of the XC164 is controlled by the internal master clock
The master clock signal
different mechanisms. The duration of master clock periods (TCMs) and their variation
(and also the derived external timing) depend on the used mechanism to generate
This influence must be regarded when calculating the timings for the XC164.
Figure 15
Note: The example for PLL operation shown in
The used mechanism to generate the master clock is selected by register PLLCON.
CPU and EBC are clocked with the CPU clock signal
same frequency as the master clock (
two:
The specification of the external timing (AC Characteristics) depends on the period of the
CPU clock, called “TCP”.
The other peripherals are supplied with the system clock signal
frequency as the CPU clock signal
Data Sheet
Phase Locked Loop Operation (1:N)
Direct Clock Drive (1:1)
Prescaler Operation (N:1)
f
CPU
f
f
f
f
f
f
the example for prescaler operation refers to a divider factor of 2:1.
OSC
MC
OSC
MC
OSC
MC
=
Timing Parameters
Definition of Internal Timing
f
MC
Generation Mechanisms for the Master Clock
/ 2. This factor is selected by bit CPSYS in register SYSCON1.
f
MC
can be generated from the oscillator clock signal
f
CPU
f
CPU
.
56
=
f
MC
Figure 15
) or can be the master clock divided by
f
CPU
. The CPU clock can have the
refers to a PLL factor of 1:4,
f
TCM
SYS
Timing Parameters
which has the same
TCM
TCM
Derivatives
V2.1, 2003-06
f
MC
f
XC164
OSC
.
f
MC
via
.
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