ISL6422 INTERSIL [Intersil Corporation], ISL6422 Datasheet - Page 11

• Manufacturer Part Number: ISL6422
• Description: Dual Output LNB Supply and Control Voltage Regulator with I2C Interface for Advanced Satellite Set-Top Box Designs
• Manufacturer: INTERSIL [Intersil Corporation]

Current Limiting
The dynamic back current limit block has five thresholds that
can be selected by the following bits of the SR.
• ISEL1H and ISEL2H
• ISEL1L and ISEL2L
• ISEL1R and ISEL2R
See Table 8 and Table 9 for threshold selection using these
bits. The DCL1 and DCL2 bits have to be set to low for this
mode of operation. In this mode, the overcurrent protection
circuit works dynamically 23µs after an overload is detected,
and the output is shutdown for a time t
Simultaneously, the OLF1 or OLF2 bit of the System
Register is set to HIGH. After this time has elapsed, the
output is resumed for a time t
device output will be current limited to a 990mA typ level. If
the overload is still detected, the protection circuit will cycle
again through t
no overload is detected, normal operation is resumed and
the OLF1 or OLF2 bit is reset to LOW. Typical t
time is 920ms as determined by an internal timer. This
dynamic operation can greatly reduce the power dissipation
in a short circuit condition, still ensuring excellent power-on
start-up in most conditions.
However, there could be some cases in which a highly
capacitive load on the output may cause a difficult start-up
when the dynamic protection is chosen. This can be solved
by initiating any power start-up in static mode (DCL = HIGH)
and then switching to the dynamic mode (DCL = LOW) after
a chosen amount of time. When in static mode, the OLF1 or
OLF2 bit goes HIGH when the peak current sense threshold
is reached and returns LOW when the overload condition is
cleared. The OLF1, OLF2, BCF1, and BCF2 bits will be LOW
at the end of initial power-on soft-start. In the static mode the
output current through the linears is limited to 990mA typ.
When a 19.3V line is connected onto a VOUT1 or VOUT2
pin that has been set to 13.3V, the linear will then enter a
dynamic back current limit state. When a dynamic back
current limit of greater that 125mA typ is sensed at the lower
FET of the linear for a period greater that 100µs, the output
is disabled for a period of 5ms and the BCF1 and BCF2 bits
are set. If the 19.3V remains connected, the output will cycle
through the ON = 100µs/OFF = 5ms. The output will recover
when the fault is removed.
Thermal Protection
This IC is protected against overheating. When the junction
temperature exceeds +150°C (typical), the step-up converter
and the linear regulator are shut off and the OTF bit of the
SR is set HIGH. Normal operation is resumed and the OTF
bit is reset LOW when the junction is cooled down to +130°C
(typical).
OFF
and t
ON
. At the end of a full t
11
ON
= 20ms. During t
OFF
, typically 900ms.
ON
ON
ON
, in which
+ t
, the
OFF
ISL6422
The FLT pin serves as an interrupt for the processor when
an over temperature, overcurrent or backwards overcurrent
fault is detected by the LNB controller or when both channels
are disabled by the I
Should the I
to ground), it is designed to power up with all control bits set
to 0 (particularly the EN1 and EN2 bits). This prevents the
device from coming back up in a state not desired by the
host controller. If the host controller sees a FLT low, it
should read the I
When it desires one or both to be high, it should re-write the
I
External Output Voltage Selection
The output voltage can be selected by the I
Additionally, the package offers two pins (SELVTOP1 and
SELVTOP2) for independent 13 through 19V output voltage
selection.
I
(Refer to Phillips I
Data transmission from the main microprocessor to the
ISL6422 and vice versa takes place through the two-wire I
bus interface, consisting of the two lines SDA and SCL. Both
SDA and SCL are bidirectional lines. They are connected to a
positive supply voltage via a pull-up resistor. (Pull-up resistors
to positive supply voltage must be externally connected.) When
the bus is free, both lines are HIGH. The output stages of
ISL6422 will have an open drain/open collector in order to
perform the wired-AND function. Data on the I
transferred up to 100Kbps in the standard mode or up to
400Kbps in the fast mode. The level of logic “0” and logic “1”
depends on the value of V
table on page 5. One clock pulse is generated for each data bit
transferred.
2
2
VSPEN1,
C to the desired state.
VSPEN2
C Bus Interface for ISL6422
0
0
0
0
1
1
1
1
2
C lose power (for example by shorting BYP pin
VTOP1,
VTOP2
2
X
X
0
1
0
0
1
1
C bits and find both EN1 and EN2 bits low.
2
C Specification, Rev. 2.1)
2
C EN1 and EN2 bits being set low.
DD
VBOT1,
TABLE 1.
VBOT2
as per the Electrical Specification
X
X
0
1
0
1
0
1
SELVTOP1,
SELVTOP2
X
X
X
X
0
0
1
1
2
2
C bus.
C bus can be
April 10, 2007
VOUT12
VOUT1,
13.3V
14.3V
18.3V
19.3V
13.3V
14.3V
18.3V
19.3V
FN9190.1
2
C