ISL6422 INTERSIL [Intersil Corporation], ISL6422 Datasheet - Page 16

• Manufacturer Part Number: ISL6422
• Description: Dual Output LNB Supply and Control Voltage Regulator with I2C Interface for Advanced Satellite Set-Top Box Designs
• Manufacturer: INTERSIL [Intersil Corporation]

Received Data (
The ISL6422 can provide to the master a copy of the system
register information via the I
mode is master-activated by sending the chip address with
the R/W bit set to 1. At the following master-generated clock
bits, the ISL6422 issues a byte on the SDA data bus line
(MSB transmitted first).
At the ninth clock bit, the MCU master can:
• Acknowledge the reception, thus starting the transmission
• Not acknowledge, thus stopping the read mode
While the whole register is read back by the microprocessor,
the following read-only bits convey diagnostic information
about the ISL6422.
• OUC1 and OUC2 (Over or Undercurrent bits)
• UV1 and UV2 (Over or Undervoltage bits)
• TPR1 and TPR2 (Tone present bits)
• OTF (Over-temperature fault bit).
NOTE: X is a “Don’t Care” for the Write mode.
SR8H
of another byte from the ISL6422.
communication.
1
1
1
1
1
1
1
1
1
1
1
1
1
1
SR8M
1
1
1
1
1
1
1
1
1
1
1
1
1
1
I
SR8L
2
C
1
1
1
1
1
1
1
1
1
1
1
1
1
1
bus READ MODE)
2
EN2
16
C bus in read mode. The read
1
1
1
1
1
1
1
1
1
1
1
1
1
0
TABLE 18. CONTROL REGISTER SR8 CONFIGURATION
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
VTOP2 VBOT2
X
0
0
0
1
1
0
0
1
1
0
0
1
1
ISL6422
X
0
0
1
0
1
0
1
0
1
0
1
0
1
Power–On I
The I
at power-on. The I
logic signal from the UVLO circuit. This signal will go HIGH
when chip power is OK. As long as this signal is LOW, the
interface will not respond to any I
system register SR1 and SR2 are initialized to all zeros, thus
keeping the power blocks disabled. Once the V
above UVLO, the POWER OK signal given to the I
interface block will be HIGH, the I
operative and the SRs can be configured by the main
microprocessor. About 400mV of hysteresis is provided in
the UVLO threshold to avoid false triggering of the power-on
reset circuit. (I
the same time as (or later than) all other I
PWM becomes valid).
SR4 is selected
VSPEN2 = SELVTOP2 = 0, V
V
VSPEN2 = SELVTOP2 = 0, V
V
VSPEN2 = SELVTOP2 = 0, V
V
VSPEN2 = SELVTOP2 = 0, V
V
VSPEN2 = 0,SELVTOP2 = 1, V
V
VSPEN2 = 0, SELVTOP2 = 1, V
V
VSPEN2 = 0, SELVTOP2 = 1, V
V
VSPEN2 = 0, SELVTOP2 = 1, V
V
VSPEN2 = 1, SELVTOP2 = X, V
V
VSPEN2 = 1, SELVTOP2 = X, V
V
VSPEN2 = 1, SELVTOP2 = X, V
V
VSPEN2 = 1, SELVTOP2 = X, V
V
PWM and Linear for channel 1 disabled
BOOST1
BOOST1
BOOST1
BOOST1
BOOST1
BOOST1
BOOST1
BOOST1
BOOST1
BOOST1
BOOST1
BOOST1
2
C interface built into the ISL6422 is automatically reset
= 13V + V
= 14V + V
= 13V + V
= 14V + V
= 18V + V
= 18V + V
= 19V + V
= 19V + V
= 13V + V
= 14V + V
= 18V + V
= 19V + V
2
2
C Interface Reset
C comes up with EN = 0; EN goes HIGH at
2
DROP
DROP
DROP
DROP
DROP
DROP
DROP
DROP
DROP
DROP
DROP
DROP
C interface block will receive a Power OK
FUNCTION
OUT1
OUT1
OUT1
OUT1
OUT1
OUT1
OUT1
OUT1
OUT1
OUT1
OUT1
OUT1
= 13V,
= 14V,
= 13V,
= 14V,
2
2
C commands and the
= 18V,
C interface becomes
= 18V,
= 19V,
= 19V,
= 13V,
= 14V,
= 18V,
= 19V,
2
C data for that
CC
2
rises
April 10, 2007
C
FN9190.1