ISL8103 INTERSIL [Intersil Corporation], ISL8103 Datasheet - Page 19

• Manufacturer Part Number: ISL8103
• Description: Three-Phase Buck PWM Controller with High Current Integrated MOSFET Drivers
• Manufacturer: INTERSIL [Intersil Corporation]

In Equations 20 and 21, P
power loss and P
loss; the gate charge (Q
particular gate to source drive voltage PVCC in the
corresponding MOSFET data sheet; I
quiescent current with no load at both drive outputs; N
and N
phase, respectively; N
phases. The I
controller without capacitive load and is typically 75mW at
300kHz.
The total gate drive power losses are dissipated among the
resistive components along the transition path and in the
bootstrap diode. The portion of the total power dissipated in
the controller itself is the power dissipated in the upper drive
path resistance, P
P
power will be dissipated by the external gate resistors (R
P
I
DR
P
P
Qg_TOT
DR_UP
FIGURE 16. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
FIGURE 15. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
PVCC
Qg_Q1
Qg_Q2
PVCC
=
Q2


3
-- - Q
2
, and in the boot strap diode, P
•
are the number of upper and lower MOSFETs per
PHASE
=
=
=
R
R
3
-- - Q
2
Q
P
LO2
G1
BOOT
HI2
Qg_Q1
G2
R
⋅
Q*
R
LO1
HI1
•
G1
VCC product is the quiescent power of the
⋅
N
PVCC F
Qg_Q2
DR_UP
Q1
⋅
+
PVCC F
LGATE
P
+
PHASE
Qg_Q2
Q
UGATE
⋅
G1
G2
is the total lower gate drive power
, the lower drive path resistance,
Qg_Q1
SW
⋅
and Q
•
19
SW
N
+
⋅
is the number of active
Q2
N
I
R
Q
Q2
⋅
G2


is the total upper gate drive
R
⋅
N
G2
G
G1
VCC
•
Q1
⋅
G
N
N
) is defined at the
R
C
PHASE
Q
PHASE
⋅
GI2
GD
BOOT
R
N
C
is the driver total
C
GI1
GD
PHASE
GS
C
GS
. The rest of the
•
S
F
S
SW
D
+
D
Q2
I
(EQ. 21)
C
(EQ. 20)
Q
Q1
DS
Q1
C
DS
G1
ISL8103
and R
the MOSFETs. Figures 15 and 16 show the typical upper
and lower gate drives turn-on transition path. The total power
dissipation in the controller itself, P
estimated as:
Current Balancing Component Selection
The ISL8103 senses the channel load current by sampling
the voltage across the lower MOSFET r
Figure 17. The ISEN pins are denoted ISEN1, ISEN2, and
ISEN3. The resistors connected between these pins and the
respective phase nodes determine the gains in the channel
current balance loop.
Select values for these resistors based on the room
temperature r
operating current, I
Equation 23.
In certain circumstances, it may be necessary to adjust the
value of one or more ISEN resistors. When the components
of one or more channels are inhibited from effectively
P
R
FIGURE 17. ISL8103 INTERNAL AND EXTERNAL CURRENT-
P
DR_LOW
ISEN
P
P
R
DR_UP
DR
BOOT
ISL8103
EXT1
G2
=
=
) and the internal gate resistors (R
P
-----------------------
50 10
r
=
=
=
=
DS ON
DR_UP
⋅



P
---------------------



R
(
SENSING CIRCUITRY
--------------------------------------
R
--------------------------------------
R
DS(ON)
Qg_Q1
G1
HI1
HI2
3
–
6
)
+
R
+
R
⋅
+
+
R
-------------
FL
N
HI1
HI2
P
I
------- -
R
R
GI1
FL
N
ISEN(n)
Q1
DR_LOW
; and the number of phases, N using
of the lower MOSFETs; the full load
EXT1
EXT2
CHANNEL N
LOWER MOSFET
+
+
R
--------------------------------------- -
R
--------------------------------------- -
R
ISEN
+
LO1
LO2
P
R
BOOT
R
R
EXT2
+
+
LO1
LO2
DR
V
R
R
IN
EXT1
EXT2
, can be roughly
+
+
=
CHANNEL N
UPPER MOSFET
-
DS(ON)
(
I
I L
R
Q






x
GI1
G2
•
•
•
r DS ON
VCC
P
---------------------
P
---------------------
I
+
L
Qg_Q1
Qg_Q2
, as shown in
and R
R
-------------
February 15, 2006
N
(
3
2
GI2
Q2
)
)
(EQ. 22)
GI2
(EQ. 23)
FN9246.0
) of