ISL8103 INTERSIL [Intersil Corporation], ISL8103 Datasheet - Page 22

• Manufacturer Part Number: ISL8103
• Description: Three-Phase Buck PWM Controller with High Current Integrated MOSFET Drivers
• Manufacturer: INTERSIL [Intersil Corporation]

The modulator transfer function is the small-signal transfer
function of V
gain, given by d
filter, with a double pole break frequency at F
F
the individual channel inductance and its DCR divided by 3
(equivalent parallel value of the three output inductors), while
C and ESR represents the total output capacitance and its
equivalent series resistance.
The compensation network consists of the error amplifier
(internal to the ISL8103) and the external R
components. The goal of the compensation network is to
provide a closed loop transfer function with high 0dB crossing
frequency (F
margin (better than 45 degrees). Phase margin is the difference
between the closed loop phase at F
equations that follow relate the compensation network’s poles,
zeros and gain to the components (R
C
locating the poles and zeros of the compensation network:
F
CE
LC
3
FIGURE 21. VOLTAGE-MODE BUCK CONVERTER
) in Figure 20 and 21. Use the following guidelines for
=
. For the purpose of this analysis, L and DCR represent
CIRCUIT
PWM
---------------------------
2π
⋅
1
COMP
L C
OUT
0
⋅
; typically 0.1 to 0.3 of F
COMPENSATION DESIGN
HALF-BRIDGE
MAX
OSCILLATOR
/V
V
COMP
OSC
E/A
DRIVE
V
R
IN
ISL8103
2
/V
. This function is dominated by a DC
C
F
+
-
VREF
+
OSC
2
-
CE
C
=
22
1
, and shaped by the output
-------------------------------- -
2π C ESR
FB
UGATE
PHASE
LGATE
VSEN
VDIFF
RGND
EXTERNAL CIRCUIT
⋅
0dB
1
SW
1
⋅
, R
R
and 180°. The
3
V
) and adequate phase
2
IN
R
, R
1
1
-R
3
C
LC
L
, C
3
3
, C
and a zero at
1
1
, C
DCR
V
-C
ESR
OUT
2
C
3
, and
ISL8103
It is recommended a mathematical model is used to plot the
loop response. Check the loop gain against the error
amplifier’s open-loop gain. Verify phase margin results and
adjust as necessary. The following equations describe the
frequency response of the modulator (G
compensation (G
G
1. Select a value for R
2. Calculate C
3. Calculate C
4. Calculate R
MOD
G
G
CL
value for R
If setting the output voltage to be equal to the reference
set voltage as shown in Figure 21, the design procedure
can be followed as presented. However, when setting the
output voltage via a resistor divider placed at the input of
the differential amplifier (as shown in Figure 6), in order
to compensate for the attenuation introduced by the
resistor divider, the obtained R
multiplied by a factor of (R
the calculations remain unchanged, as long as the
compensated R
at 0.1 to 0.75 of F
desired number). The higher the quality factor of the output
filter and/or the higher the ratio F
frequency (to maximize phase boost at F
such that F
times F
frequency. Change the numerical factor to reflect desired
placement of this pole. Placement of F
frequency helps reduce the gain of the compensation
network at high frequency, in turn reducing the HF ripple
component at the COMP pin and minimizing resultant
duty cycle jitter.
R
C
C
R
C
FB
2
1
2
3
3
f ( )
f ( )
f ( )
=
=
=
=
=
=
=
-------------------------------------------- -
d
---------------------------------------------- -
2π R
------------------------------------------------------- -
2π R
--------------------- -
------------------------------------------------ -
2π R
=
F
----------- - 1
F
V
MAX
SW
SW
LC
G
d
----------------------------- -
--------------------------------------------------- - ⋅
s f ( ) R
OSC
⋅
R
⋅
⋅
⋅
MAX
------------------------------------------------------------------------------------------------------------------------ -
(
MOD
1
1
V
1
P2
). F
–
2
1
2
2
+
2
3
3
OSC
⋅
⋅
+
V
such that F
⋅
⋅
for desired converter bandwidth (F
⋅
⋅
s f ( ) R
such that F
such that F
1
FB
⋅
s f ( ) R
1
0.5 F
C
is placed below F
0.7 F
R
f ( ) G
IN
C
SW
1
V
1
1
1
⋅
2
) and closed-loop response (G
IN
⋅
⋅
⋅
⋅
⋅
(
LC
⋅
⋅
⋅
F
value is used.
F
C
F
represents the per-channel switching
⋅
LC
0
CE
2
1
1
FB
LC
SW
---------------------------------------------------------------------------------------------------------- -
1
1
3
(to adjust, change the 0.5 factor to
⋅
+
+
+
⋅
(1kΩ to 5kΩ, typically). Calculate
C
f ( )
–
C
C
s f ( )
s f ( )
Z1
1
P1
1
Z2
3
2
)
)
is placed at a fraction of the F
⋅
P
⋅
is placed at F
is placed at F
⋅



(
(
+R
1
where s f ( )
R
ESR
1
1
+
SW
2
S
CE
+
+
s f ( ) R
)/R
value needs be
R
s f ( ) ESR C
+
/F
,
(typically, 0.5 to 1.0
3
DCR
P
⋅
) C
LC
. The remainder of
MOD
⋅
⋅
2
, the lower the F
P2
⋅
LC
3
CE
LC
=
) C



), feedback
⋅
-------------------- -
C
C
lower in
2π f j
).
. Calculate C
.
⋅
1
1
February 15, 2006
+
+
⋅
⋅ ⋅
s
C
C
CL
2
2
0
2
f ( ) L C



).
):



FN9246.0
⋅
LC
⋅
Z1
3
,