ISL8200AM INTERSIL [Intersil Corporation], ISL8200AM Datasheet - Page 18

• Manufacturer Part Number: ISL8200AM
• Description: Complete Current Share 10A DC/DC Power Module
• Manufacturer: INTERSIL [Intersil Corporation]

By connecting the FSYNC_IN pin to an external square pulse
waveform (such as the CLKOUT signal, typically 50% duty cycle
from another ISL8200AM), the ISL8200AM will synchronize its
switching frequency to the fundamental frequency of the input
waveform. The voltage range on the FSYNC_IN pin is V
V
leading edge of the CLKOUT signal with the falling edge of
Channel 1’s PWM clock signal. CLKOUT is not available until the
PLL locks.
The locking time is typically 210µs for F
released for a soft-start cycle until FSYNC_IN is stabilized and the
PLL is in locking. It is recommended to connect all EN pins
together in multiphase configuration.
The loss of a synchronization signal for 13 clock cycles causes
the IC to be disabled until the PLL returns locking, at which point
a soft-start cycle is initiated and normal operation resumes.
Holding FSYNC_IN low will disable the IC.
Setting Relative Phase-Shift on CLKOUT
Depending upon the voltage level at PH_CNTRL, set by the VCC
resistor divider output, the ISL8200AM operates with CLKOUT
phase shifted, as shown in Table 2. The phase shift is latched as
V
Layout Guide
To achieve stable operation, low losses, and good thermal
performance, some layout considerations are necessary, which
are illustrated in Figures 35 and 36.
• The ground connection between PGND1 (pin 15) and PGND
CC
CC
(pin 18) should be a solid ground plane under the module.
29% to 45% of V
45% to 62% of V
PH_CNTRL RANGE
. The Frequency Synchronization feature will synchronize the
raises above POR so it cannot be changed on the fly.
<29% of V
62% to V
1500
1400
1300
1200
1100
1000
DECODING
900
800
700
FIGURE 34. RFS-ext vs SWITCHING FREQUENCY
0
CC
CC
CC
CC
100
PHASE FOR CLKOUT WRT
TABLE 2.
18
CHANNEL 1
RFS-ext (kΩ)
200
120°
180°
-60°
90°
SW
300
= 700kHz. EN is not
PH_CNTRL
REQUIRED
15% V
37% V
53% V
CC
400
V
ISL8200AM
CC
/2 to
CC
CC
CC
• Place a high frequency ceramic capacitor between (1) PVIN
• Use large copper areas for power path (PVIN, PGND, VOUT) to
• Keep the trace connection to the feedback resistor short.
• Use remote sensed traces to the regulation point to achieve a
• Avoid routing any sensitive signal traces, such as the VOUT and
• FSYNC_IN is a sensitive pin. If it is not used for receiving an
The recommended layout considerations for operating multiple
modules in parallel follows the single-phase guidelines as well as
these additional points:
• Orient VOUT towards the load on the same layer and connect
• Place modules such that pins 1-11 point away from power
• Keep remote sensing traces separate, and connect only at the
FIGURE 35. RECOMMENDED LAYOUT FOR SINGLE PHASE SETUP
and PGND (pin 18) and (2) a 10µF between PVCC and PGND1
(pin 15) as close to the module as possible to minimize high
frequency noise. High frequency ceramic capacitors close to
the module between VOUT and PGND will help to minimize
noise at the output ripple.
minimize conduction loss and thermal stress. Also, use
multiple vias to connect the power planes in different layers.
tight output voltage regulation, and keep them in parallel.
Route a trace from VSEN_REM- to a location near the load
ground, and a trace from feedback resistor to the point-of-load
where the tight output voltage is desire.
VSENREM- sensing point near the PHASE pin or any other
noise-prone areas.
external synchronization signal, then keep the trace
connecting to the pin short. A bypass capacitor value of 100pF,
connecting between FSYNC_IN pin and GND1, can help to
bypass the noise sensitivity on the pin.
with thick direct copper etch directly to minimize the loss.
pads (PD1-4) so that signal busses (EN, ISHARE,
CLKOUT-to-FSYNCIN) can be routed without going under the
module. Run them along the perimeter as in Figure 36.
regulation point. Four separate traces for VSEN_REM- and
RFBT (which stands for remote feedback) as in the example in
Figure 36.
CPVCC
CEN
PV
IN
CIN
PGND
COUT
RFBT
V
OUT
Load GND
September 13, 2012
VOUT
To
To
FN8271.2