ADT7460ARQZ-RL7 ONSEMI [ON Semiconductor], ADT7460ARQZ-RL7 Datasheet - Page 20

• Manufacturer Part Number: ADT7460ARQZ-RL7
• Description: dBCOOL Remote Thermal Monitor and Fan Controller
• Manufacturer: ONSEMI [ON Semiconductor]

SMBALERT Interrupt Behavior
interrupt can be generated for out−of−limit conditions. It is
important to note how the SMBALERT output and status
bits behave when writing interrupt handler software.
status bits behave. Once a limit is exceeded, the
corresponding status bit is set to 1. The status bit remains set
until the error condition subsides and the status register is
read. The status bits are referred to as sticky since they
remain set until read by software. This ensures that an
out−of−limit event cannot be missed if software is polling
the device periodically. Note that the SMBALERT output
remains low for the entire duration that a reading is
out−of−limit and until the status register has been read. This
has implications on how software handles the interrupt.
Handling SMBALERT Interrupts
interrupts, it is recommend to handle the SMBALERT
interrupt as follows:
HIGH LIMIT
TEMPERATURE
STATUS BIT
SMBALERT
“STICKY”
The ADT7460 can be polled for status, or an SMBALERT
Figure 34 shows how the SMBALERT output and sticky
To prevent the system from being tied up servicing
Figure 34. SMBALERT and Status Bit Behavior
1. Detect the SMBALERT assertion.
2. Enter the interrupt handler.
3. Read the status registers to identify the interrupt
4. Mask the interrupt source by setting the
5. Take the appropriate action for a given interrupt
6. Exit the interrupt handler.
7. Periodically poll the status registers. If the
source.
appropriate mask bit in the interrupt mask registers
(Reg. 0x74, 0x75).
source.
interrupt status bit has cleared, reset the
corresponding interrupt mask bit to 0. This causes
the SMBALERT output and status bits to behave
as shown in Figure 35.
TEMP BACK IN LIMIT
(STATUS BIT STAYS SET)
(TEMP BELOW LIMIT)
CLEARED ON READ
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ADT7460
20
Masking Interrupt Sources
0x74 and 0x75. These allow individual interrupt sources to
be masked out to prevent SMBALERT interrupts. Note that
masking an interrupt source prevents only the SMBALERT
output from being asserted; the appropriate status bit is set
as normal.
HIGH LIMIT
TEMPERATURE
STATUS BIT
SMBALERT
Table 22. Interrupt Mask Register 1 (Reg. 0x74)
Table 23. Interrupt Mask Register 2 (Reg. 0x75)
Figure 35. How Masking the Interrupt Source Affects
“STICKY”
Bit
Bit
Interrupt Mask Registers 1 and 2 are located at Addresses
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Mnemonic
Mnemonic
FAN4
FAN3
FAN2
FAN1
2.5 V
OOL
VCC
OVT
R2T
R1T
D2
D1
LT
−
−
−
SMBALERT Output
1 masks SMBALERT for any alert
condition flagged in Status Register 2.
1 masks SMBALERT for Remote 2
temperature.
1 masks SMBALERT for local
temperature.
1 masks SMBALERT for Remote 1
temperature.
Unused
1 masks SMBALERT for the V
channel.
Unused
1 masks SMBALERT for the 2.5 V
channel.
1 masks SMBALERT for Diode 2 errors.
1 masks SMBALERT for Diode 1 errors.
1 masks SMBALERT for Fan 4 failure. If
the TACH4 pin is being used as the
THERM input, this bit masks
SMBALERT for a THERM event.
1 masks SMBALERT for Fan 3.
1 masks SMBALERT for Fan 2.
1 masks SMBALERT for Fan 1.
1 masks SMBALERT for
overtemperature (exceeding THERM
limits).
Unused
TEMP BACK IN LIMIT
(STATUS BIT STAYS SET)
INTERRUPT
MASK BIT SET
Description
Description
(TEMP BELOW LIMIT)
CLEARED ON READ
(SMBALERT REARMED)
INTERRUPT MASK BIT
CLEARED
CC