ADT7460ARQZ-RL7 ONSEMI [ON Semiconductor], ADT7460ARQZ-RL7 Datasheet - Page 22

• Manufacturer Part Number: ADT7460ARQZ-RL7
• Description: dBCOOL Remote Thermal Monitor and Fan Controller
• Manufacturer: ONSEMI [ON Semiconductor]

If the THERM timer is read during a THERM assertion
Generating SMBALERT Interrupts from THERM Events
programmable THERM limit has been exceeded. This
allows the systems designer to ignore brief, infrequent
THERM assertions while capturing longer THERM events.
Register 0x7A is the THERM limit register. This 8−bit
register allows a limit from 0 seconds (first THERM
Configuring the Desired THERM Behavior
The ADT7460 can generate SMBALERTs when a
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1. Configure the THERM input.
2. Select the desired fan behavior for THERM events.
3. Select whether THERM events should generate
THERM assertion is occurring).
bit is set.
The contents of the timer are cleared.
Bit 0 of the THERM timer is set to 1 (since a
The THERM timer increments from 0.
If the THERM limit (Reg. 0x7A) = 0x00, the F4P
Setting Bit 1 (THERM ENABLE) of Configuration
Register 3 (Reg. 0x78) enables the THERM
monitoring function.
Setting Bit 2 (BOOST bit) of Configuration
Register 3 (Reg. 0x78) causes all fans to run at
100% duty cycle whenever THERM is asserted.
This allows fail−safe system cooling. If this bit = 0,
the fans run at their current settings and are not
affected by THERM events.
SMBALERT interrupts.
Bit 5 (F4P) of Mask Register 2 (Reg. 0x75), when
set, masks out SMBALERTs when the THERM
limit value is exceeded. This bit should be cleared
THERM LIMIT
(REG. 0x7A)
Figure 38. Functional Diagram of the ADT7460 THERM Monitoring Circuitry
728.32ms
364.16ms
182.08ms
91.04ms
45.52ms
22.76ms
2.914s
1.457s
0
1
2
3
4
5
6
7
COMPARATOR
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ADT7460
22
CLEARED
ON READ
7 6 5 4 3 2 1 0
assertion) to 5.825 seconds to be set before an SMBALERT
is generated. The THERM timer value is compared with the
contents of the THERM limit register. If the THERM timer
value exceeds the THERM limit value, the F4P bit (Bit 5) of
Status Register 2 is set and an SMBALERT is generated.
Note that the F4P bit (Bit 5) of Mask Register 2 (Reg. 0x75)
masks out SMBALERTs if this bit is set to 1, although the
F4P bit of Interrupt Status Register 2 is still set if the
THERM limit is exceeded.
timer, limit, and associated circuitry. Writing 0x00 to the
THERM limit register (Reg. 0x7A) causes SMBALERT to
be generated on the first THERM assertion. A THERM limit
of 0x01 generates an SMBALERT once cumulative
THERM assertions exceed 45.52 ms.
IN
LATCH
RESET
Figure 38 is a functional block diagram of the THERM
4. Select a suitable THERM limit value.
5. Select a THERM monitoring time.
OUT
if SMBALERTs based on THERM events are
required.
This value determines whether an SMBALERT is
generated on the first THERM assertion, or only if
a cumulative THERM assertion time limit is
exceeded. A value of 0x00 causes an SMBALERT
to be generated on the first THERM assertion.
This is how often OS or BIOS level software
checks the THERM timer. For example, BIOS
could read the THERM timer once an hour to
determine the cumulative THERM assertion time.
If, for example, the total THERM assertion time is
<22.76 ms in Hour 1, >182.08 ms in Hour 2, and
>5.825 s in Hour 3, this can indicate that system
performance is degrading significantly since
1 = MASK
MASK REGISTER 2
STATUS REGISTER 2
F4P BIT (BIT 5)
(REG. 0x75)
F4P BIT (BIT 5)
THERM TIMER CLEARED ON READ
2.914s
1.457s
728.32ms
364.16ms
182.08ms
91.04ms
45.52ms
22.76ms
THERM TIMER
(REG. 0x79)
SMBALERT
THERM