ADT7460ARQZ-RL7 ONSEMI [ON Semiconductor], ADT7460ARQZ-RL7 Datasheet - Page 34

• Manufacturer Part Number: ADT7460ARQZ-RL7
• Description: dBCOOL Remote Thermal Monitor and Fan Controller
• Manufacturer: ONSEMI [ON Semiconductor]

1. This register becomes read−only when the Configuration Register 1 lock bit is set to 1. Further attempts to write to this register have no effect.
Table 45. Register 0x37 — Dynamic T
Bit No.
<2:0>
<5:3>
<7:6>
Mnemonic
CYR1
CYR2
CYL
R/W
R/W
R/W
R/W
3−Bit Remote 1 Cycle Value. These three bits define the delay time between making subsequent
T
cycles. The system has associated thermal time constants that need to be found to optimize the
response of fans and the control loop.
3−Bit Local Temperature Cycle Value. These three bits define the delay time between making
subsequent T
number of monitoring cycles. The system has associated thermal time constants that need to
be found to optimize the response of fans and the control loop.
2 LSBs of 3−Bit Remote 2 Cycle Value. The MSB of the 3−bit code resides in Dynamic T
Control Register 1 (Reg. 0x36). These three bits define the delay time between making
subsequent T
of monitoring cycles. The system has associated thermal time constants that need to be found
to optimize the response of fans and the control loop.
MIN
Bits
Bits
Bits
000
001
010
011
100
101
110
000
001
010
011
100
101
110
000
001
010
011
100
101
110
111
111
111
MIN
adjustments in the control loop for the Remote 1 channel, in terms of number of monitoring
Control Register 2 (Power−On Default = 0x00)
4 Cycles (0.5 s)
8 Cycles (1 s)
16 Cycles (2 s)
32 Cycles (4 s)
64 Cycles (8 s)
128 Cycles (16 s)
256 Cycles (32 s)
512 Cycles (64 s)
4 Cycles (0.5 s)
8 Cycles (1 s)
16 Cycles (2 s)
32 Cycles (4 s)
64 Cycles (8 s)
128 Cycles (16 s)
256 Cycles (32 s)
512 Cycles (64 s)
4 Cycles (0.5 s)
8 Cycles (1 s)
16 Cycles (2 s)
32 Cycles (4 s)
64 Cycles (8 s)
128 Cycles (16 s)
256 Cycles (32 s)
512 Cycles (64 s)
MIN
MIN
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adjustments in the control loop for local temperature channel, in terms of
adjustments in the control loop for the Remote 2 channel, in terms of number
ADT7460
Decrease Cycle
Decrease Cycle
Decrease Cycle
34
Description
8 Cycles (1 s)
16 Cycles (2 s)
32 Cycles (4 s)
64 Cycles (8 s)
128 Cycles (16 s)
256 Cycles (32 s)
512 Cycles (64 s)
1024 Cycles (128 s)
8 Cycles (1 s)
16 Cycles (2 s)
32 Cycles (4 s)
64 Cycles (8 s)
128 Cycles (16 s)
256 Cycles (32 s)
512 Cycles (64 s)
1024 Cycles (128 s)
8 Cycles (1 s)
16 Cycles (2 s)
32 Cycles (4 s)
64 Cycles (8 s)
128 Cycles (16 s)
256 Cycles (32 s)
512 Cycles (64 s)
1024 Cycles (128 s)
(Note 1)
Increase Cycle
Increase Cycle
Increase Cycle
MIN