SSTUM32866EC/G NXP [NXP Semiconductors], SSTUM32866EC/G Datasheet - Page 21
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SSTUM32866EC/G
Manufacturer Part Number
SSTUM32866EC/G
Description
1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2-1G RDIMM applications
Manufacturer
NXP [NXP Semiconductors]
Datasheet
1.SSTUM32866ECG.pdf
(28 pages)
NXP Semiconductors
SSTUM32866_1
Product data sheet
11.4 Partial parity out load circuit and voltage measurement information
V
All input pulses are supplied by generators having the following characteristics:
PRR
Fig 23. Voltage waveforms, open-drain output LOW-to-HIGH transition time with respect to
Fig 24. Partial parity out load circuit
Fig 25. Partial parity out voltage waveforms; propagation delay times with respect to clock
DD
= 1.8 V
(1) C
10 MHz; Z
clock inputs
V
t
V
inputs
PLH
T
i(p-p)
L
includes probe and jig capacitance.
= 0.5V
and t
= 600 mV.
0.1 V.
PHL
DD
o
waveform 2
.
= 50 ; input slew rate = 1 V/ns
are the same as t
CK
CK
output
timing
inputs
Rev. 01 — 29 June 2007
output
1.8 V DDR2-1G configurable registered buffer with parity
DUT
t
V
PLH
OUT
PD
ICR
.
V
t
LH
ICR
C
0.15 V
L
= 5 pF
(1)
V
ICR
20 %, unless otherwise specified.
t
V
V
PHL
ICR
T
test point
R
002aaa654
L
002aaa503
= 1 k
SSTUM32866
002aaa375
V
i(p-p)
V
V
V
0 V
OH
OL
V
OH
i(p-p)
© NXP B.V. 2007. All rights reserved.
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