SSTUM32866EC/G NXP [NXP Semiconductors], SSTUM32866EC/G Datasheet - Page 7

• Manufacturer Part Number: SSTUM32866EC/G
• Description: 1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2-1G RDIMM applications
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
Table 3.
[1]
[2]
SSTUM32866_1
Product data sheet
Symbol
GND
V
VREF
CK
CK
C0
C1
RESET
CSR
DCS
D1 to D25
DODT
DCKE
PAR_IN
Q1 to Q25,
Q1A to Q14A,
Q1B to Q14B
PPO
QCS, QCSA,
QCSB
QODT, QODTA,
QODTB
QCKE,
QCKEA,
QCKEB
QERR
n.c.
DNU
DD
Data inputs = D2, D3, D5, D6, D8 to D25 when C0 = 0 and C1 = 0.
Data inputs = D2, D3, D5, D6, D8 to D14 when C0 = 0 and C1 = 1.
Data inputs = D1 to D6, D8 to D10, D12, D13 when C0 = 1 and C1 = 1.
Depends on configuration. See
Pin description
Pin
B3, B4, D3, D4, F3, F4,
H3, H4, K3, K4, M3,
M4, P3, P4
A4, C3, C4, E3, E4,
G3, G4, J3, J4, L3, L4,
N3, N4, R3, R4, T4
A3, T3
H1
J1
G6
G5
G2
J2
H2
[2]
[2]
[2]
G1
[2]
A2
[2]
[2]
[2]
D2
[2]
[2]
6.2 Pin description
Figure
4,
Figure
Type
ground input
1.8 V nominal
0.9 V nominal
differential input
differential input
LVCMOS inputs
LVCMOS input
SSTL_18 input
SSTL_18 input
SSTL_18 input
SSTL_18 input
SSTL_18 input
1.8 V CMOS
outputs
1.8 V CMOS
output
1.8 V CMOS
output
1.8 V CMOS
output
1.8 V CMOS
output
open-drain
output
-
-
5, and
Rev. 01 — 29 June 2007
Figure 6
1.8 V DDR2-1G configurable registered buffer with parity
for ball number.
Description
ground
power supply voltage
input reference voltage
positive master clock input
negative master clock input
Configuration control inputs; Register A or Register B and
1 : 1 mode or 1 : 2 mode select.
Asynchronous reset input (active LOW). Resets registers and
disables VREF data and clock.
Chip select inputs (active LOW). Disables D1 to D25
outputs switching when both inputs are HIGH.
Data input. Clocked in on the crossing of the rising edge of
CK and the falling edge of CK.
The outputs of this register bit will not be suspended by the
DCS and CSR control.
The outputs of this register bit will not be suspended by the
DCS and CSR control.
Parity input. Arrives one clock cycle after the corresponding
data input.
Data outputs that are suspended by the DCS and CSR
control.
Partial parity out. Indicates odd parity of inputs D1 to D25.
Data output that will not be suspended by the DCS and CSR
control.
Data output that will not be suspended by the DCS and CSR
control.
Data output that will not be suspended by the DCS and CSR
control.
Output error bit (active LOW). Generated one clock cycle
after the corresponding data output.
Not connected. Ball present but no internal connection to the
die.
Do not use. Inputs are in standby-equivalent mode and
outputs are driven LOW.
[3]
SSTUM32866
© NXP B.V. 2007. All rights reserved.
[1]
7 of 28
[1]