SAK-XC161CJ-16F20F INFINEON [Infineon Technologies AG], SAK-XC161CJ-16F20F Datasheet - Page 25

• Manufacturer Part Number: SAK-XC161CJ-16F20F
• Description: 16-Bi t Single-Chip Microcontroller Preliminary
• Manufacturer: INFINEON [Infineon Technologies AG]

Preliminary
The EBC also controls accesses to resources connected to the on-chip LXBus. The
LXBus is an internal representation of the external bus and allows accessing integrated
peripherals and modules in the same way as external components.
The TwinCAN module is connected and accessed via the LXBus.
3.3
The main core of the CPU consists of a 5-stage execution pipeline with a 2-stage
instruction-fetch pipeline, a 16-bit arithmetic and logic unit (ALU), a 32-bit/40-bit multiply
and accumulate unit (MAC), a register-file providing three register banks, and dedicated
SFRs. The ALU features a multiply and divide unit, a bit-mask generator, and a barrel
shifter.
Figure 4
Based on these hardware provisions, most of the XC161’s instructions can be executed
in just one machine cycle which requires 25 ns at 40 MHz CPU clock. For example, shift
and rotate instructions are always processed during one machine cycle independent of
Data Sheet
Internal Program Memory
SRAM
MAC
CPU
Prefetch Unit
Branch Unit
Multiply Unit
MAH
IDX0
IDX1
FIFO
QX0
QX1
+/-
+/-
Central Processing Unit (CPU)
CPU Block Diagram
Return Stack
CPUCON1
CPUCON2
MCW
MRW
MSW
CSP
MAL
CPUID
QR0
QR1
+/-
IP
PMU
DMU
IFU
Division Unit
Multiply Unit
DPP0
DPP1
DPP2
DPP3
Zeros
MDC
PSW
MDH
Peripheral-Bus
Injection/Exception
Bit-Mask-Gen.
Handler
Barrel-Shifter
VECSEG
SPSEG
STKOV
STKUN
Ones
MDL
TFR
SP
+/-
21
ADU
ALU
System-Bus
RF
System-Bus
Buffer
GPRs
2-Stage
5-Stage
R15
R14
CP
R1
R0
Prefetch
Pipeline
GPRs
Pipeline
R15
R14
R1
R0
GPRs
R15
R14
R1
R0
WB
IPIP
Functional Description
Derivatives
V1.0, 2002-03
address
data in
DPRAM
data out
GPRs
R15
R14
R1
R0
XC161