SAK-XC161CJ-16F20F INFINEON [Infineon Technologies AG], SAK-XC161CJ-16F20F Datasheet - Page 63

• Manufacturer Part Number: SAK-XC161CJ-16F20F
• Description: 16-Bi t Single-Chip Microcontroller Preliminary
• Manufacturer: INFINEON [Infineon Technologies AG]

Preliminary
5
5.1
The internal operation of the XC161 is controlled by the internal master clock
The master clock signal
different mechanisms. The duration of master clock periods (TCMs) and their variation
(and also the derived external timing) depend on the used mechanism to generate
This influence must be regarded when calculating the timings for the XC161.
Figure 13
Note: The example for PLL operation shown in
The used mechanism to generate the master clock is selected by register PLLCON.
CPU and EBC are clocked with the CPU clock signal
same frequency as the master clock (
two:
The specification of the external timing (AC Characteristics) depends on the period of the
CPU clock, called “TCP”.
The other peripherals are supplied with the system clock signal
frequency as the CPU clock signal
Data Sheet
f
CPU
I
I
I
I
I
I
the example for prescaler operation refers to a divider factor of 2:1.
=
Timing Parameters
Definition of Internal Timing
f
MC
Generation Mechanisms for the Master Clock
/ 2. This factor is selected by bit CPSYS in register SYSCON1.
f
MC
can be generated from the oscillator clock signal
f
CPU
f
CPU
.
59
=
f
MC
Figure 13
) or can be the master clock divided by
f
CPU
. The CPU clock can have the
refers to a PLL factor of 1:4,
f
TCM
SYS
Timing Parameters
which has the same
TCM
TCM
Derivatives
V1.0, 2002-03
f
MC
f
XC161
OSC
.
f
MC
via
.